From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1E6ngY-0001WI-Pp for qemu-devel@nongnu.org; Sun, 21 Aug 2005 07:08:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1E6ngU-0001Uw-HC for qemu-devel@nongnu.org; Sun, 21 Aug 2005 07:08:17 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1E6ngT-0001RI-Ly for qemu-devel@nongnu.org; Sun, 21 Aug 2005 07:08:13 -0400 Received: from [65.74.133.11] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1E6nbf-0005R7-Nr for qemu-devel@nongnu.org; Sun, 21 Aug 2005 07:03:16 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [patch] NPTL/TLS support Date: Sun, 21 Aug 2005 12:02:47 +0100 References: <200508141653.25261.paul@codesourcery.com> <430850FE.9080306@bellard.org> In-Reply-To: <430850FE.9080306@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200508211202.48579.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > > - The Arm magic kernel code page. This is used on recent Arm kernels to > > provide efficient access to kernel/CPU features. For example atomic > > operations, and reading the TLS register (which may or may not be a real > > hardware register). This is simplified version of the VDSO used on recent > > x86 and ppc kernels. > > On i386 there are AUXENTs to define the address of the VDSO page > (AT_SYSINFO and AT_SYSINFO_EHDR). If it was supported by the ARM glibc, > it would avoid some hacks you need to do to intercept calls to it. Can > you check that ? Arm does not [yet] use a full VDSO. As Arm is primarily aimed at embedded targets it was decided that the overhead of a VDSO was undesirable. In particular a fixed page mapping means an application can use shifter tricks to generate the address and avoid the PLT indirection. e.g.: __aeabi_read_tp: mov r0, #0xffff0fff sub pc, r0, #31 Paul