From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1EGJb9-0007Zq-Q2 for qemu-devel@nongnu.org; Fri, 16 Sep 2005 13:02:03 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1EGJb6-0007YM-TI for qemu-devel@nongnu.org; Fri, 16 Sep 2005 13:02:02 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1EGJb6-0007Wu-4L for qemu-devel@nongnu.org; Fri, 16 Sep 2005 13:02:00 -0400 Received: from [65.74.133.11] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1EGJZ5-0008Uo-QH for qemu-devel@nongnu.org; Fri, 16 Sep 2005 12:59:56 -0400 From: Paul Brook Date: Fri, 16 Sep 2005 17:59:49 +0100 MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_GovKDukGawiAG8A" Message-Id: <200509161759.50348.paul@codesourcery.com> Subject: [Qemu-devel] [patch] Arm hwcaps Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --Boundary-00=_GovKDukGawiAG8A Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline The attached patch implements the Arm AT_HWCAP AUXV entry. This allows libc to determine what CPU instruction sets are available. Paul --Boundary-00=_GovKDukGawiAG8A Content-Type: text/x-diff; charset="us-ascii"; name="patch.qemu_hwcap" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="patch.qemu_hwcap" Index: linux-user/elfload.c =================================================================== RCS file: /cvsroot/qemu/qemu/linux-user/elfload.c,v retrieving revision 1.27 diff -u -p -r1.27 elfload.c --- linux-user/elfload.c 21 Aug 2005 10:12:28 -0000 1.27 +++ linux-user/elfload.c 16 Sep 2005 16:40:03 -0000 @@ -91,6 +91,28 @@ static inline void init_thread(struct ta #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 +#define DLINFO_ARCH_ITEMS 1 +enum +{ + ARM_HWCAP_ARM_SWP = 1 << 0, + ARM_HWCAP_ARM_HALF = 1 << 1, + ARM_HWCAP_ARM_THUMB = 1 << 2, + ARM_HWCAP_ARM_26BIT = 1 << 3, + ARM_HWCAP_ARM_FAST_MULT = 1 << 4, + ARM_HWCAP_ARM_FPA = 1 << 5, + ARM_HWCAP_ARM_VFP = 1 << 6, + ARM_HWCAP_ARM_EDSP = 1 << 7, +}; + +#define ARM_HWCAPS (ARM_HWCAP_ARM_SWP | ARM_HWCAP_ARM_HALF \ + | ARM_HWCAP_ARM_THUMB | ARM_HWCAP_ARM_FAST_MULT \ + | ARM_HWCAP_ARM_FPA | ARM_HWCAP_ARM_VFP) + +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_HWCAP, ARM_HWCAPS); \ +} while (0) + #endif #ifdef TARGET_SPARC --Boundary-00=_GovKDukGawiAG8A--