Re: [Qemu-devel] QNX 6.3 and a PCI network card

["M. Warner Losh" <imp@bsdimp.com>]

In message: <7f45d9390511181225t404ae527q@mail.gmail.com>
            Shaun Jackman <sjackman@gmail.com> writes:
: 2005/11/18, M. Warner Losh <imp@bsdimp.com>:
: > I've run into issues with qemu's emulation of the RTL8129 that is
: > claimed with changes I made to the FreeBSD ed driver.  While I've
: > fixed the ed driver to be more tolerent of the old emulation, I've
: > fixed these issues in qemu with some patches that were posted here a
: > while ago.  Basically, it adds support for the id registers as well as
: > the status registers that a RTL8129 driver might expect to be there
: > (my patches always reports 10/baseT full duplex).
: >
: > These patches are in the FreeBSD ports collection right now.  I can
: > dig them up if there's a need.  I hope they get applied to qemu soon.
: >
: > Warner
: 
: I'd very much appreciate your sending me the patch. If it solves my
: issue with QNX, I'll see if I can get it incorporated into the Debian
: package.

Since it is short, here is the patch that I have in the FreeBSD ports
tree for this issue.  It works sufficiently for FreeBSD's RTL
subdriver of ed to be happy.

Warner


--- qemu/hw/ne2000.c~	Thu Oct 13 16:33:39 2005
+++ qemu/hw/ne2000.c	Thu Oct 13 16:33:47 2005
@@ -47,7 +47,9 @@
 #define EN0_CRDAHI	0x09	/* high byte, current remote dma address RD */
 #define EN0_RSARHI	0x09	/* Remote start address reg 1 */
 #define EN0_RCNTLO	0x0a	/* Remote byte count reg WR */
+#define EN0_RTL8029ID0	0x0a	/* Realtek ID byte #1 RD */
 #define EN0_RCNTHI	0x0b	/* Remote byte count reg WR */
+#define EN0_RTL8029ID1	0x0b	/* Realtek ID byte #2 RD */
 #define EN0_RSR		0x0c	/* rx status reg RD */
 #define EN0_RXCR	0x0c	/* RX configuration reg WR */
 #define EN0_TXCR	0x0d	/* TX configuration reg WR */
@@ -64,6 +66,11 @@
 #define EN2_STARTPG	0x21	/* Starting page of ring bfr RD */
 #define EN2_STOPPG	0x22	/* Ending page +1 of ring bfr RD */
 
+#define EN3_CONFIG0	0x33
+#define EN3_CONFIG1	0x34
+#define EN3_CONFIG2	0x35
+#define EN3_CONFIG3	0x36
+
 /*  Register accessed at EN_CMD, the 8390 base addr.  */
 #define E8390_STOP	0x01	/* Stop and reset the chip */
 #define E8390_START	0x02	/* Start the chip, clear reset */
@@ -385,6 +392,21 @@
         case EN2_STOPPG:
             ret = s->stop >> 8;
             break;
+	case EN0_RTL8029ID0:
+	    ret = 0x50;
+	    break;
+	case EN0_RTL8029ID1:
+	    ret = 0x43;
+	    break;
+	case EN3_CONFIG0:
+	    ret = 0;		/* 10baseT media */
+	    break;
+	case EN3_CONFIG2:
+	    ret = 0x40;		/* 10baseT active */
+	    break;
+	case EN3_CONFIG3:
+	    ret = 0x40;		/* Full duplex */
+	    break;
         default:
             ret = 0x00;
             break;