From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1EmId4-0003h0-Kn
	for qemu-devel@nongnu.org; Tue, 13 Dec 2005 17:28:14 -0500
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1EmId2-0003dO-84
	for qemu-devel@nongnu.org; Tue, 13 Dec 2005 17:28:13 -0500
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1EmId1-0003cq-R6
	for qemu-devel@nongnu.org; Tue, 13 Dec 2005 17:28:11 -0500
Received: from [65.74.133.11] (helo=mail.codesourcery.com)
	by monty-python.gnu.org with esmtp
	(TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1EmIez-0006CH-Hf
	for qemu-devel@nongnu.org; Tue, 13 Dec 2005 17:30:13 -0500
From: Paul Brook <paul@codesourcery.com>
Date: Tue, 13 Dec 2005 22:27:30 +0000
MIME-Version: 1.0
Content-Type: Multipart/Mixed;
  boundary="Boundary-00=_Tr0nDvCuQshb/ZB"
Message-Id: <200512132227.31113.paul@codesourcery.com>
Subject: [Qemu-devel] [patch] Arm bugs
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

--Boundary-00=_Tr0nDvCuQshb/ZB
Content-Type: text/plain;
  charset="us-ascii"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

The attached patch fixes two bugs in the Arm system emulation.

Firstly do_interrupt wasn't switching to Arm mode properly.

Secondly the #if in cpu_reset is the wrong way round. Linux works mostly by 
chance: the early boot code does a SWI, and the exception vector happens to 
drop it back at a convenient place in the loader.

Paul

--Boundary-00=_Tr0nDvCuQshb/ZB
Content-Type: text/x-diff; charset="us-ascii"; name="patch.qemu_thumb_excp"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
	filename="patch.qemu_thumb_excp"

=== target-arm/helper.c
==================================================================
--- target-arm/helper.c	(revision 1912)
+++ target-arm/helper.c	(local)
@@ -162,10 +162,11 @@
     }
     switch_mode (env, new_mode);
     env->spsr = cpsr_read(env);
-    /* Switch to the new mode, and clear the thumb bit.  */
+    /* Switch to the new mode, and switch to Arm mode.  */
     /* ??? Thumb interrupt handlers not implemented.  */
-    env->uncached_cpsr = (env->uncached_cpsr & ~(CPSR_M | CPSR_T)) | new_mode;
+    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
     env->uncached_cpsr |= mask;
+    env->thumb = 0;
     env->regs[14] = env->regs[15] + offset;
     env->regs[15] = addr;
     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
=== target-arm/translate.c
==================================================================
--- target-arm/translate.c	(revision 1912)
+++ target-arm/translate.c	(local)
@@ -2431,10 +2431,10 @@
 void cpu_reset(CPUARMState *env)
 {
 #if defined (CONFIG_USER_ONLY)
+    env->uncached_cpsr = ARM_CPU_MODE_USR;
+#else
     /* SVC mode with interrupts disabled.  */
     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
-#else
-    env->uncached_cpsr = ARM_CPU_MODE_USR;
 #endif
     env->regs[15] = 0;
 }

--Boundary-00=_Tr0nDvCuQshb/ZB--