From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1EoOHQ-0007AI-TI for qemu-devel@nongnu.org; Mon, 19 Dec 2005 11:54:33 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1EoOHO-000786-Vz for qemu-devel@nongnu.org; Mon, 19 Dec 2005 11:54:32 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1EoOHO-00077m-Ep for qemu-devel@nongnu.org; Mon, 19 Dec 2005 11:54:30 -0500 Received: from [66.93.172.17] (helo=nevyn.them.org) by monty-python.gnu.org with esmtp (TLS-1.0:RSA_AES_128_CBC_SHA:16) (Exim 4.34) id 1EoOKM-0007kA-VW for qemu-devel@nongnu.org; Mon, 19 Dec 2005 11:57:35 -0500 Date: Mon, 19 Dec 2005 11:53:35 -0500 From: Daniel Jacobowitz Subject: Re: [Qemu-devel] Re: ARM page crossing inside insn? (Re: ARM ethernet fixes) Message-ID: <20051219165335.GA24866@nevyn.them.org> References: <200512150000.07159.paul@codesourcery.com> <200512181651.02705.paul@codesourcery.com> <20051218172558.GA446@nevyn.them.org> <20051218.104216.28085930.imp@bsdimp.com> <20051218175430.GA1580@nevyn.them.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: ananaza@iki.fi, qemu-devel@nongnu.org On Mon, Dec 19, 2005 at 05:24:48PM +0200, Antti P Miettinen wrote: > Antti P Miettinen writes: > > but anyway - how would the ldm register update be made atomic? Or > > should the restart be able to continue in the middle? How are the > > atomicity issues handled in qemu? > > I wonder how the ARM implementations handle it.. > > The below is a quick test how the atomicity could be achieved with > shadow registers. Is this a feasible approach? The diff is not a > proper/complete patch - I just wanted to see whether it makes a > different. It does - the firefox compile proceeds.. You don't need anything near this complicated: if the register being set is the base register, copy it into T2 instead of overwriting the base register. Then at the end, if the base register was loaded, copy T2 into the base register. That's all the atomicity you need; the instruction is being restarted after the base register was clobbered. -- Daniel Jacobowitz CodeSourcery, LLC