From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: "Schwarz, Konrad" <konrad.schwarz@siemens.com>
Subject: Re: [Qemu-devel] Questions on ARM port
Date: Tue, 14 Mar 2006 14:21:20 +0000 [thread overview]
Message-ID: <200603141421.21027.paul@codesourcery.com> (raw)
In-Reply-To: <ECDC9C7BC7809340842C0E7FCF48C393EFCB89@MCHP7IEA.ww002.siemens.net>
> Basically, r3 is initialized by <start+8> (to 0x80000, in my case). The
> next instruction (at <start+12>) switches the mode to FIQ. After single
> steping over this in QEMU (via GDB si), r3 no longer contains what it
> had before (0x80000), instead, it is set to 0. If I manually fix this
> (via set $r3=0x80000), then at the next mode switch (at <start+28>) r3
> is changed incorrectly to zero again.
>
> Is this my fault or what is happening?
It's a big in the qemu FIQ bank switching code. Fixed now.
Paul
next prev parent reply other threads:[~2006-03-14 14:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-03-14 13:28 [Qemu-devel] Questions on ARM port Schwarz, Konrad
2006-03-14 14:21 ` Paul Brook [this message]
-- strict thread matches above, loose matches on Subject: below --
2006-03-15 8:55 Schwarz, Konrad
2006-03-15 14:19 ` Paul Brook
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