[Qemu-devel] Questions on ARM port

[Qemu-devel] Questions on ARM port

[Schwarz, Konrad]

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Hello,
 
the Newlib crt0.S file for ARM starts off by initializing the stack
pointers for the different ARM modes (FIQ, IRQ, supervisor, etc.) with
the help of r3.
 
e.g., this is the disassembly as produced by GDB:
 
Dump of assembler code for function start:
0x00008224 <start+0>:   ldr     r3, [pc, #208]  ; 0x82fc <$d+4>
0x00008228 <start+4>:   cmp     r3, #0  ; 0x0
0x0000822c <start+8>:   ldreq   r3, [pc, #196]  ; 0x82f8 <$d>
0x00008230 <start+12>:  msr     CPSR_c, #209    ; 0xd1
0x00008234 <start+16>:  mov     sp, r3
0x00008238 <start+20>:  sub     r10, sp, #4096  ; 0x1000
0x0000823c <start+24>:  mov     r3, r10
0x00008240 <start+28>:  msr     CPSR_c, #215    ; 0xd7
0x00008244 <start+32>:  mov     sp, r3
...
 
Basically, r3 is initialized by <start+8> (to 0x80000, in my case).  The
next instruction (at <start+12>) switches the mode to FIQ.  After single
steping over this in QEMU (via GDB si), r3 no longer contains what it
had before (0x80000), instead, it is set to 0.  If I manually fix this
(via set $r3=0x80000), then at the next mode switch (at <start+28>) r3
is changed incorrectly to zero again.
 
Is this my fault or what is happening?
 
I am invoking qemu as
 
    arm-softmmu/qemu-system-arm -S -s -M altera_excalibur -m 64 -net
none -nographic -kernel
../projekte/L6/node-arm/libsys/test-io/libsys_test_uart -monitor null
-parallel null -serial null
 
(where altera_excalibur is a machine that I have added and would like to
debug).
 
Regards,
 
Konrad Schwarz

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Re: [Qemu-devel] Questions on ARM port

[Paul Brook]

> Basically, r3 is initialized by <start+8> (to 0x80000, in my case).  The
> next instruction (at <start+12>) switches the mode to FIQ.  After single
> steping over this in QEMU (via GDB si), r3 no longer contains what it
> had before (0x80000), instead, it is set to 0.  If I manually fix this
> (via set $r3=0x80000), then at the next mode switch (at <start+28>) r3
> is changed incorrectly to zero again.
>
> Is this my fault or what is happening?

It's a big in the qemu FIQ bank switching code. Fixed now.

Paul

RE: [Qemu-devel] Questions on ARM port

[Schwarz, Konrad]

> -----Original Message-----
> From: Paul Brook [mailto:paul@codesourcery.com] 
> Sent: Tuesday, March 14, 2006 3:21 PM
> To: qemu-devel@nongnu.org
> Cc: Schwarz, Konrad
> Subject: Re: [Qemu-devel] Questions on ARM port
> 
> > Basically, r3 is initialized by <start+8> (to 0x80000, in 
> my case).  
> > The next instruction (at <start+12>) switches the mode to 
> FIQ.  After 
> > single steping over this in QEMU (via GDB si), r3 no longer 
> contains 
> > what it had before (0x80000), instead, it is set to 0.  If 
> I manually 
> > fix this (via set $r3=0x80000), then at the next mode switch (at 
> > <start+28>) r3 is changed incorrectly to zero again.
> >
> > Is this my fault or what is happening?
> 
> It's a big in the qemu FIQ bank switching code. Fixed now.
> 
> Paul 

Oh, great!

How do I get the patch?

Konrad 

Re: [Qemu-devel] Questions on ARM port

[Paul Brook]

> > It's a bug in the qemu FIQ bank switching code. Fixed now.
>
> Oh, great!
>
> How do I get the patch?

http://cvs.savannah.nongnu.org/viewcvs/qemu/target-arm/helper.c?root=qemu&r1=1.4&r2=1.5

Paul