From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FSDCl-00078S-Kg for qemu-devel@nongnu.org; Sat, 08 Apr 2006 09:10:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FSDCj-00074x-Px for qemu-devel@nongnu.org; Sat, 08 Apr 2006 09:10:19 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FSDCj-00074i-Kw for qemu-devel@nongnu.org; Sat, 08 Apr 2006 09:10:17 -0400 Received: from [65.74.133.6] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1FSDGv-0002G2-FG for qemu-devel@nongnu.org; Sat, 08 Apr 2006 09:14:37 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Translation cache sizes Date: Sat, 8 Apr 2006 14:10:11 +0100 References: <3ACA6D63-C6FD-11DA-9D2F-003065C7D858@mandriva.com> In-Reply-To: <3ACA6D63-C6FD-11DA-9D2F-003065C7D858@mandriva.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200604081410.12303.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Saturday 08 April 2006 13:43, Gwenole Beauchesne wrote: > Hi, > > > With those changes in place, the same boot-to-kdm process > > requires only about 570000 translations to be made, and 2 > > cache flushes to happen. Of course the cost is an extra > > 48M of memory use. > > I faced a similar problem in Basilisk II. MacOS 8.x had a tendency to > invalidate the code cache approx. 1000 times per second. My poor > K6-2/300 was suffering a lot. About 45% of the time was dedicated to > compilation of code, and desktop experience was very sluggish. Then, I > came up with a very simple idea I named "lazy cache flush". Performance > increased by 76% and compilation time dropped below 10%, desktop > experience was very smooth. I will give you more contemporary results > hereunder. Qemu already does this. Initially it does it on a per-page basis (writes to a given physical memory page will invalidate all code on that page), and for frequently contested pages it does more fine-grained locking. x86 doesn't have explicit icache invalidate instructions, the icache is architecturally defined to be coherent after every jump instructions. Paul