Re: [Qemu-devel] MIPS interrupt handling

[Thiemo Seufer <ths@networkno.de>]

Fabrice Bellard wrote:
> I just looked at the MIPS file target-mips/op_helper.c and I don't 
> understand why IRQs need to be handled in op_helper.c:do_mtc0() with reg 
> = 12.

Register 12 is the cp0_status register, it defines which interrupts are
masked/enabled/disabled. Btw, I have a patch which moves this to op.c,
this should improve performance a bit (and avoids the TB stop for
most mtc0 writes).

> IMHO, the corresponding code should be deleted because the TB is 
> forced to terminate after mtc0 so that the IRQs can be handled in the 
> main loop in cpu-exec.c.
> 
> Moreover, clearing CPU_INTERRUPT_HARD in do_mtc0() is almost surely a bug !

Somehow the interrupt assert has to be prevented when St0_IE is cleared.
That's probably also a job for the main loop, but there may be a race
condition (haven't looked yet). Empirically, it works well. :-)


Thiemo