* [Qemu-devel] [PATCH 4/8] Mips improvements
@ 2006-05-15 1:24 Thiemo Seufer
0 siblings, 0 replies; only message in thread
From: Thiemo Seufer @ 2006-05-15 1:24 UTC (permalink / raw)
To: qemu-devel
Hello All,
This patch fixes wrong bitmasks for CP0_Context and CP0_EntryHi.
Thiemo
Index: qemu-work/target-mips/helper.c
===================================================================
--- qemu-work.orig/target-mips/helper.c 2006-05-07 23:41:39.000000000 +0100
+++ qemu-work/target-mips/helper.c 2006-05-07 23:43:38.000000000 +0100
@@ -231,7 +231,7 @@
env->CP0_Context = (env->CP0_Context & 0xff800000) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi =
- (env->CP0_EntryHi & 0xFF) | (address & 0xFFFFF000);
+ (env->CP0_EntryHi & 0xFF) | (address & 0xFFFFE000);
env->exception_index = exception;
env->error_code = error_code;
ret = 1;
Index: qemu-work/target-mips/op_helper.c
===================================================================
--- qemu-work.orig/target-mips/op_helper.c 2006-05-07 23:41:39.000000000 +0100
+++ qemu-work/target-mips/op_helper.c 2006-05-07 23:43:38.000000000 +0100
@@ -342,7 +342,7 @@
rn = "EntryLo1";
break;
case 4:
- val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0);
+ val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
old = env->CP0_Context;
env->CP0_Context = val;
rn = "Context";
@@ -366,7 +366,7 @@
rn = "Count";
break;
case 10:
- val = T0 & 0xFFFFF0FF;
+ val = T0 & 0xFFFFE0FF;
old = env->CP0_EntryHi;
env->CP0_EntryHi = val;
/* If the ASID changes, flush qemu's TLB. */
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2006-05-15 1:24 [Qemu-devel] [PATCH 4/8] Mips improvements Thiemo Seufer
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