From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FzXUr-0000so-Lz for qemu-devel@nongnu.org; Sun, 09 Jul 2006 07:30:45 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FzXUp-0000sZ-48 for qemu-devel@nongnu.org; Sun, 09 Jul 2006 07:30:44 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FzXUo-0000sQ-Tz for qemu-devel@nongnu.org; Sun, 09 Jul 2006 07:30:42 -0400 Received: from [65.74.133.6] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1FzXVf-0007W7-KS for qemu-devel@nongnu.org; Sun, 09 Jul 2006 07:31:35 -0400 From: Paul Brook Subject: Re: [Qemu-devel] add 'monitor' and 'mwait' instruction (update) Date: Sun, 9 Jul 2006 12:30:23 +0100 References: <44AD28AA.7050301@armiento.net> <1AC114B9-DB82-4F97-B0A8-831233CA2ECE@gmx.de> <44B10282.3060707@armiento.net> In-Reply-To: <44B10282.3060707@armiento.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200607091230.24239.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "R. Armiento" > > Problem is, at the moment I've no idea, how we could achieve this memory > > monitoring in a safe and simple way in user space. > > I'm trying to read up on monitor and mwait. Apparently mwait puts the > processor in low-power wait mode, waiting for a memory write in some > select area defined by monitor; and as I am new to this I'm not sure if > I have understood all sources from where such a memory write can come > from while the processor is asleep. One source, I suppose, is from other > processors in an SMP setup? Another source may be DMA? Does this mean > that it is safe to emulate wmait as hlt if neiter SMP or DMA is used? > (Qemu hardware doesn't support DMA, right?) qemu hardware does support DMA, but I don't think this matters. By my reading DMA writes don't need to wake mwait. The exact wording is "store operation", which I'd expect to mean execution of a store instruction (by a different CPU). So for UP systems mwait can be implemented the same as HLT, except that it raises an exception if state hasn't been initialized by monitor. Paul