From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] ARM load/store multiple bug
Date: Sun, 10 Sep 2006 00:43:08 +0100 [thread overview]
Message-ID: <200609100043.09455.paul@codesourcery.com> (raw)
In-Reply-To: <Pine.LNX.4.63.0609092307540.3197@buttercup.gerph.org>
> ---8<---
> if (n != 1)
> gen_op_addl_T1_im(-((n - 1) * 4));
> }
> }
> j = 0;
> /* Insert something like gen_op_bicl_T1_im(3); here */
> for(i=0;i<16;i++) {
> if (insn & (1 << i)) {
> if (insn & (1 << 20)) {
> ---8<---
This is not sufficient. It breaks base register writeback.
I'll also note that the behavior is dependent on alignment traps being
disabled (and unaligned access on some cores). ie. for linux user mode
emulation the current behavior is acceptable.
Paul
next prev parent reply other threads:[~2006-09-09 23:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-09 22:19 [Qemu-devel] ARM load/store multiple bug Justin Fletcher
2006-09-09 23:43 ` Paul Brook [this message]
2006-09-10 10:43 ` Justin Fletcher
2006-09-10 16:46 ` Fabrice Bellard
2006-09-10 17:15 ` Paul Brook
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