From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GMCTj-0002u0-HK for qemu-devel@nongnu.org; Sat, 09 Sep 2006 19:43:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GMCTh-0002s2-To for qemu-devel@nongnu.org; Sat, 09 Sep 2006 19:43:15 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GMCTh-0002ry-Pe for qemu-devel@nongnu.org; Sat, 09 Sep 2006 19:43:13 -0400 Received: from [65.74.133.4] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GMCUc-0001GX-O5 for qemu-devel@nongnu.org; Sat, 09 Sep 2006 19:44:11 -0400 From: Paul Brook Subject: Re: [Qemu-devel] ARM load/store multiple bug Date: Sun, 10 Sep 2006 00:43:08 +0100 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609100043.09455.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > ---8<--- > if (n != 1) > gen_op_addl_T1_im(-((n - 1) * 4)); > } > } > j = 0; > /* Insert something like gen_op_bicl_T1_im(3); here */ > for(i=0;i<16;i++) { > if (insn & (1 << i)) { > if (insn & (1 << 20)) { > ---8<--- This is not sufficient. It breaks base register writeback. I'll also note that the behavior is dependent on alignment traps being disabled (and unaligned access on some cores). ie. for linux user mode emulation the current behavior is acceptable. Paul