From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GPQAh-0000r3-5M for qemu-devel@nongnu.org; Mon, 18 Sep 2006 16:56:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GPQAf-0000m3-Hk for qemu-devel@nongnu.org; Mon, 18 Sep 2006 16:56:54 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GPQAf-0000lY-C1 for qemu-devel@nongnu.org; Mon, 18 Sep 2006 16:56:53 -0400 Received: from [65.74.133.4] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GPQDZ-0001CK-Mo for qemu-devel@nongnu.org; Mon, 18 Sep 2006 16:59:53 -0400 From: Paul Brook Subject: Re: [Qemu-devel] bug in ARM thumb usermode emulation Date: Mon, 18 Sep 2006 21:56:48 +0100 References: <564d96fb0609181305n14cf7afexefd50b5cd724428d@mail.gmail.com> <200609182117.00519.paul@codesourcery.com> <564d96fb0609181343m45ff7a76p5a110ef5c896b30a@mail.gmail.com> In-Reply-To: <564d96fb0609181343m45ff7a76p5a110ef5c896b30a@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609182156.49174.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > What must be done for implementing TLS + multithread in qemu? Maybe I can > help. * Implement the TLS syscalls (futexes and the architecture specific bits). There's a patch for clone() here: https://nowt.dyndns.org/patch.qemu_nptl * Fix all the bits of qemu that aren't threadsafe (mainly the TB cache IIRC). * Fix guest atomic operations, and make sure guest coherency/ordering guaranteed are honoured, even which not guaranteed natively by the host. Note that this only applies to usermode emulation. Full system emulation works fine because this is all handled by the guest kernel, exactly the same as on real hardware. Paul