From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GWOKB-0007dH-Ov for qemu-devel@nongnu.org; Sat, 07 Oct 2006 22:23:31 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GWOK9-0007cp-7l for qemu-devel@nongnu.org; Sat, 07 Oct 2006 22:23:30 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GWOK9-0007cZ-0I for qemu-devel@nongnu.org; Sat, 07 Oct 2006 22:23:29 -0400 Received: from [65.74.133.4] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GWORN-0003RG-6k for qemu-devel@nongnu.org; Sat, 07 Oct 2006 22:30:57 -0400 From: Paul Brook Subject: Re: [Qemu-devel] why do qem/arm not clear CPU_INTERRUPT_HARD bit of env->interrupt_request automatically? Date: Sun, 8 Oct 2006 03:23:21 +0100 References: <84e41160610071115t75b4ec55vbe656630d5ab9373@mail.gmail.com> In-Reply-To: <84e41160610071115t75b4ec55vbe656630d5ab9373@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200610080323.21706.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Saturday 07 October 2006 19:15, Donald Liew wrote: > i'm reading qemu-system-arm code and trying to add some more > evaluation boards support for it. in the 0.8.2 source code i found > something i can't understand, when handling interrupts all other > targets clears this bit after calling do_interrupt, however the arm > target doesn't do this, why? won't this cause problems like redundant > interrupts? any special consideration about this? I this this is the correct behavior. The nIRQ line is level triggered. spurious interrupts are avoided because do_interrupt sets the CPSR_I flag. During normal operation theguest OS will clear the IRQ condition (by masking the interrupt on the PIC or device) before clearing the CPSE_I flag, so it doesn't matter what we do. Consider the case where the guest OS were to clear CPSR_F without touching the IRQ line. In this case we would expect annother IRQ exception to be taken immediately. If (as you suggest above) we cleared CPU_INTERRUPT_HARD in cpu_exec then the IRQ would not be taken until something re-raised the IRQ line. Paul