From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Gf2rn-0006vR-Tu for qemu-devel@nongnu.org; Tue, 31 Oct 2006 18:18:00 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Gf2rm-0006u8-5a for qemu-devel@nongnu.org; Tue, 31 Oct 2006 18:17:59 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Gf2rl-0006tp-Pm for qemu-devel@nongnu.org; Tue, 31 Oct 2006 18:17:57 -0500 Received: from [71.162.243.5] (helo=grelber.thyrsus.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1Gf2rl-0003Mu-Ig for qemu-devel@nongnu.org; Tue, 31 Oct 2006 18:17:57 -0500 From: Rob Landley Subject: Re: [Qemu-devel] qemu vs gcc4 Date: Tue, 31 Oct 2006 18:17:49 -0500 References: <45391B22.1050608@palmsource.com> <200610311153.00334.rob@landley.net> <200610311902.21898.paul@codesourcery.com> In-Reply-To: <200610311902.21898.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200610311817.50024.rob@landley.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On Tuesday 31 October 2006 2:02 pm, Paul Brook wrote: > As an example take the arm instruction > > add, r0, r1, r2, lsl #2 > > This is equivalent to the C expression > > r0 = r1 + (r2 << 2) ... > When fully converted to the new system this would become: > > int tmp = gen_new_qreg(); /* Allocate a temporary reg. */ > /* gen_im32 is a helper that allocates a new qreg and > initializes it to an immediate value. */ > gen_op_add32(tmp, QREG_R2, gen_im32(2)); > gen_op_add32(QREG_R0, QREG_R1, tmp); I forgot to ask: Where's the shift? I think the above code means you generate an immediate value (the 2), add it to R2 with the result going in a spill register, and then add the spill register to R1, with the result going to R0. Should that middle line be some kind of gen_op_lshift32() instead of gen_op_add32()? Do qregs ever get freed? (I'm guessing gen_new_qreg() lasts until the end of the translated block, and then the next block has its own set of qregs?) Rob -- "Perfection is reached, not when there is no longer anything to add, but when there is no longer anything to take away." - Antoine de Saint-Exupery