From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GmWnS-0006AI-1q for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:40:26 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GmWnQ-00069k-V2 for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:40:25 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GmWnQ-00069e-Rj for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:40:24 -0500 Received: from [193.7.176.60] (helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GmWnP-0001C5-Qo for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:40:24 -0500 Received: from lagash (unknown [195.71.97.210]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bawue.net (Postfix) with ESMTP id 9B9A9BBC7F for ; Tue, 21 Nov 2006 15:41:50 +0100 (CET) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GmWnd-0003Wt-DT for qemu-devel@nongnu.org; Tue, 21 Nov 2006 14:40:37 +0000 Date: Tue, 21 Nov 2006 14:40:37 +0000 Message-ID: <20061121144037.GD12745@networkno.de> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="raC6veAxrt5nqIoY" Content-Disposition: inline From: Thiemo Seufer Subject: [Qemu-devel] [PATCH 3/6] A cumulative MIPS patchset Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --raC6veAxrt5nqIoY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello All, this patch adds more devices to the MIPS system emulation, most importantly a RTC emulation which e.g. keeps timestamps on a linux filesystem sane. Thiemo Index: qemu-work/Makefile.target =================================================================== --- qemu-work.orig/Makefile.target 2006-11-20 01:18:46.000000000 +0000 +++ qemu-work/Makefile.target 2006-11-20 01:21:22.000000000 +0000 @@ -358,7 +358,8 @@ endif ifeq ($(TARGET_ARCH), mips) VL_OBJS+= mips_r4k.o dma.o vga.o serial.o i8254.o i8259.o ide.o -#VL_OBJS+= #pckbd.o fdc.o m48t59.o +VL_OBJS+= pckbd.o ps2.o mc146818rtc.o +#VL_OBJS+= #fdc.o m48t59.o endif ifeq ($(TARGET_BASE_ARCH), sparc) ifeq ($(TARGET_ARCH), sparc64) Index: qemu-work/hw/mips_r4k.c =================================================================== --- qemu-work.orig/hw/mips_r4k.c 2006-11-20 01:21:18.000000000 +0000 +++ qemu-work/hw/mips_r4k.c 2006-11-20 01:21:22.000000000 +0000 @@ -1,7 +1,8 @@ #include "vl.h" #define BIOS_FILENAME "mips_bios.bin" -//#define BIOS_FILENAME "system.bin" +#define LINUX_BOOT_FILENAME "linux_boot.bin" + #define KERNEL_LOAD_ADDR 0x80010000 #define INITRD_LOAD_ADDR 0x80800000 @@ -13,6 +14,7 @@ extern FILE *logfile; +static RTCState *rtc_state; static PITState *pit; static void pic_irq_request(void *opaque, int level) @@ -110,6 +112,35 @@ cpu_mips_update_count(env, 1, 0); } +#define REG_EQUIPMENT_BYTE 0x14 +#define REG_IBM_CENTURY_BYTE 0x32 +#define REG_IBM_PS2_CENTURY_BYTE 0x37 + +static inline int to_bcd(RTCState *s, int a) +{ + return ((a / 10) << 4) | (a % 10); +} + +static void cmos_init(int ram_size, int boot_device, BlockDriverState **hd_table) +{ + RTCState *s = rtc_state; + int val; + time_t ti; + struct tm *tm; + + /* set the CMOS date */ + time(&ti); + if (rtc_utc) + tm = gmtime(&ti); + else + tm = localtime(&ti); + rtc_set_date(s, tm); + + val = to_bcd(s, (tm->tm_year / 100) + 19); + rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); + rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); +} + static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, uint32_t val) { @@ -251,12 +282,15 @@ cpu_mips_clock_init(env); cpu_mips_irqctrl_init(); + rtc_state = rtc_init(0x70, 8); + /* Register 64 KB of ISA IO space at 0x14000000 */ isa_mmio_init(0x14000000, 0x00010000); isa_mem_base = 0x10000000; isa_pic = pic_init(pic_irq_request, env); pit = pit_init(0x40, 0); + serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); isa_vga_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size); @@ -274,6 +308,11 @@ for(i = 0; i < 2; i++) isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], bs_table[2 * i], bs_table[2 * i + 1]); + + kbd_init(); + DMA_init(1); + + cmos_init(ram_size, boot_device, bs_table); } QEMUMachine mips_machine = { --raC6veAxrt5nqIoY Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="qemu.drow-halt-reboot" Content-Transfer-Encoding: quoted-printable Date: Sat, 11 Nov 2006 20:02:40 -0500 =46rom: Daniel Jacobowitz To: qemu-devel@nongnu.org Subject: [Qemu-devel] MIPS halt / reboot The MIPS kernel already has a reset/halt device for qemu (arch/mips/qemu/q-reset.c). I have no idea at all where this came =66rom, but hey, it seems sensible enough to me so I implemented it in qemu. This requires a bit of additional mucking around, since MIPS doesn't currently have any BIOS support, so I made the reset vector reload any specified kernel and initrd. Works in my Debian rootfs; very handy for automated benchmarking. --=20 Daniel Jacobowitz CodeSourcery --- hw/mips_r4k.c | 144 +++++++++++++++++++++++++++++++++----------= ----- target-mips/cpu.h | 8 ++ target-mips/translate.c | 10 +++ 3 files changed, 116 insertions(+), 46 deletions(-) Index: qemu-work/hw/mips_r4k.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/hw/mips_r4k.c 2006-11-15 22:40:28.000000000 +0000 +++ qemu-work/hw/mips_r4k.c 2006-11-15 22:41:14.000000000 +0000 @@ -110,6 +110,93 @@ cpu_mips_update_count(env, 1, 0); } =20 +static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + if ((addr & 0xffff) =3D=3D 0 && val =3D=3D 42) + qemu_system_reset_request (); + else if ((addr & 0xffff) =3D=3D 4 && val =3D=3D 42) + qemu_system_shutdown_request (); +} + +static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) +{ + return 0; +} + +static CPUWriteMemoryFunc *mips_qemu_write[] =3D { + &mips_qemu_writel, + &mips_qemu_writel, + &mips_qemu_writel, +}; + +static CPUReadMemoryFunc *mips_qemu_read[] =3D { + &mips_qemu_readl, + &mips_qemu_readl, + &mips_qemu_readl, +}; + +static int mips_qemu_iomemtype =3D 0; + +void load_kernel (CPUState *env, int ram_size, const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename) +{ + int64_t entry =3D 0; + long kernel_size, initrd_size; + + kernel_size =3D load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); + if (kernel_size >=3D 0) + env->PC =3D entry; + else { + kernel_size =3D load_image(kernel_filename, + phys_ram_base + KERNEL_LOAD_ADDR + VIRT_T= O_PHYS_ADDEND); + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + env->PC =3D KERNEL_LOAD_ADDR; + } + + /* load initrd */ + initrd_size =3D 0; + if (initrd_filename) { + initrd_size =3D load_image(initrd_filename, + phys_ram_base + INITRD_LOAD_ADDR + VIRT_T= O_PHYS_ADDEND); + if (initrd_size =3D=3D (target_ulong) -1) { + fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", + initrd_filename); + exit(1); + } + } + + /* Store command line. */ + if (initrd_size > 0) { + int ret; + ret =3D sprintf(phys_ram_base + (16 << 20) - 256, + "rd_start=3D0x%08x rd_size=3D%li ", + INITRD_LOAD_ADDR, + initrd_size); + strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); + } + else { + strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); + } + + *(int *)(phys_ram_base + (16 << 20) - 260) =3D tswap32 (0x12345678); + *(int *)(phys_ram_base + (16 << 20) - 264) =3D tswap32 (ram_size); +} + +static void main_cpu_reset(void *opaque) +{ + CPUState *env =3D opaque; + cpu_reset(env); + + if (env->kernel_filename) + load_kernel (env, env->ram_size, env->kernel_filename, + env->kernel_cmdline, env->initrd_filename); +} =20 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, DisplayState *ds, const char **fd_filename, int snapsh= ot, @@ -117,19 +204,24 @@ const char *initrd_filename) { char buf[1024]; - int64_t entry =3D 0; unsigned long bios_offset; int ret; CPUState *env; - long kernel_size; int i; =20 env =3D cpu_init(); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); + qemu_register_reset(main_cpu_reset, env); =20 /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); =20 + if (!mips_qemu_iomemtype) { + mips_qemu_iomemtype =3D cpu_register_io_memory(0, mips_qemu_read, + mips_qemu_write, NULL); + } + cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); + /* Try to load a BIOS image. If this fails, we continue regardless, but initialize the hardware ourselves. When a kernel gets preloaded we also initialize the hardware, since the BIOS wasn't @@ -146,38 +238,13 @@ buf); } =20 - kernel_size =3D 0; if (kernel_filename) { - kernel_size =3D load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); - if (kernel_size >=3D 0) - env->PC =3D entry; - else { - kernel_size =3D load_image(kernel_filename, - phys_ram_base + KERNEL_LOAD_ADDR + VI= RT_TO_PHYS_ADDEND); - if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", - kernel_filename); - exit(1); - } - env->PC =3D KERNEL_LOAD_ADDR; - } - - /* load initrd */ - if (initrd_filename) { - if (load_image(initrd_filename, - phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND) - =3D=3D (target_ulong) -1) { - fprintf(stderr, "qemu: could not load initial ram disk '%s= '\n",=20 - initrd_filename); - exit(1); - } - } - - /* Store command line. */ - strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); - /* FIXME: little endian support */ - *(int *)(phys_ram_base + (16 << 20) - 260) =3D tswap32 (0x12345678= ); - *(int *)(phys_ram_base + (16 << 20) - 264) =3D tswap32 (ram_size); + load_kernel (env, ram_size, kernel_filename, kernel_cmdline, + initrd_filename); + env->ram_size =3D ram_size; + env->kernel_filename =3D kernel_filename; + env->kernel_cmdline =3D kernel_cmdline; + env->initrd_filename =3D initrd_filename; } =20 /* Init internal devices */ Index: qemu-work/target-mips/cpu.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/cpu.h 2006-11-15 22:41:04.000000000 +0000 +++ qemu-work/target-mips/cpu.h 2006-11-15 22:41:14.000000000 +0000 @@ -182,7 +182,6 @@ uint32_t CP0_ErrorEPC; uint32_t CP0_DESAVE; /* Qemu */ - struct QEMUTimer *timer; /* Internal timer */ int interrupt_request; jmp_buf jmp_env; int exception_index; @@ -213,6 +212,13 @@ int halted; /* TRUE if the CPU is in suspend state */ =20 CPU_COMMON + + int ram_size; + const char *kernel_filename; + const char *kernel_cmdline; + const char *initrd_filename; + + struct QEMUTimer *timer; /* Internal timer */ }; =20 #include "cpu-all.h" Index: qemu-work/target-mips/translate.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/translate.c 2006-11-15 22:41:04.000000000 +0= 000 +++ qemu-work/target-mips/translate.c 2006-11-15 22:41:14.000000000 +0000 @@ -2425,7 +2425,16 @@ if (!env) return NULL; cpu_exec_init(env); + cpu_reset(env); + return env; +} + +void cpu_reset (CPUMIPSState *env) +{ + memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + tlb_flush(env, 1); + /* Minimal init */ env->PC =3D 0xBFC00000; #if defined (MIPS_USES_R4K_TLB) @@ -2456,5 +2465,4 @@ #ifdef MIPS_USES_FPU env->fcr0 =3D MIPS_FCR0;=09 #endif - return env; } --raC6veAxrt5nqIoY--