Re: SV: [Qemu-devel] ARM CPSR and conditional instructions

[Paul Brook <paul@codesourcery.com>]

> However, we have seen that the condition bits in CPSR differers compared to
> one other arm instruction set simulator, running the same binary. This
> indicate for us that there might be something wrong i QEMU (translate.c
> op.c for ARM). However, it is not proven yet.

The only restriction it that you can't set the N and Z bits simultaneously. 
This never occurs under normal circumstances, only if you directly modify the 
CPSR value.

> However, our understanding for the situation would improve if the strategy
> for simulating the conditional execution of ARM instructions is understood.
>
> Is a conditional ARM instruction treated as a branch-point, an end marker
> for a TB? If not, jumps qemu within a TB?
> Is it possible to describe the strategy with a reasonable effort? I would
> be very greatfull.

A TB is terminated at a branch, and at some instructions that modify system 
state (eg. moves to system registers, and the svc and bkpt instructions). 
Conditional instructions do not terminate the TB unless they are conditional  
branches.

Paul