From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Gnk3C-0007EF-2O for qemu-devel@nongnu.org; Fri, 24 Nov 2006 18:01:42 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Gnk39-0007C7-Pa for qemu-devel@nongnu.org; Fri, 24 Nov 2006 18:01:41 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Gnk39-0007Bh-FM for qemu-devel@nongnu.org; Fri, 24 Nov 2006 18:01:39 -0500 Received: from [199.232.41.67] (helo=mx20.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1Gnjy5-0000vf-WB for qemu-devel@nongnu.org; Fri, 24 Nov 2006 17:56:26 -0500 Received: from [65.74.133.4] (helo=mail.codesourcery.com) by mx20.gnu.org with esmtp (Exim 4.52) id 1GnGe2-0006QO-KY for qemu-devel@nongnu.org; Thu, 23 Nov 2006 10:37:46 -0500 From: Paul Brook Subject: Re: SV: [Qemu-devel] ARM CPSR and conditional instructions Date: Thu, 23 Nov 2006 15:28:59 +0000 References: <80846442723677@lycos-europe.com> In-Reply-To: <80846442723677@lycos-europe.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200611231529.01318.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?iso-8859-1?q?Torbj=F6rn?= Andersson > However, we have seen that the condition bits in CPSR differers compared to > one other arm instruction set simulator, running the same binary. This > indicate for us that there might be something wrong i QEMU (translate.c > op.c for ARM). However, it is not proven yet. The only restriction it that you can't set the N and Z bits simultaneously. This never occurs under normal circumstances, only if you directly modify the CPSR value. > However, our understanding for the situation would improve if the strategy > for simulating the conditional execution of ARM instructions is understood. > > Is a conditional ARM instruction treated as a branch-point, an end marker > for a TB? If not, jumps qemu within a TB? > Is it possible to describe the strategy with a reasonable effort? I would > be very greatfull. A TB is terminated at a branch, and at some instructions that modify system state (eg. moves to system registers, and the svc and bkpt instructions). Conditional instructions do not terminate the TB unless they are conditional branches. Paul