From: Thiemo Seufer <ths@networkno.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 6/6, UPDATE] A cumulative MIPS patchset
Date: Wed, 29 Nov 2006 14:50:41 +0000 [thread overview]
Message-ID: <20061129145041.GA2777@networkno.de> (raw)
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[The previous patch had a broken MIPS32R2 bitops implementation,
and was apparently too big to make it to the list. I retry now
with a compressed attachment.]
Hello All,
this patch adds support for all mandatory MIPS32R2 instructions,
rationalizes the instruction decoding to check always 32-bit words,
reduces the number of magic constants in the code, adds a few bits
which make eventually implementation of MIPS64 support and optional
MIPS32 features easier.
The emulated CPU still identifies itself as a MIPS32(R1) 4Kc.
Currently it doesn't throw a RI exception for R2 instructions, this
is useful for Linux userland emulation, and also follows the current
policy which doesn't distinguish between MIPS32R1 instructions and
those of earlier ISAs.
Thiemo
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next reply other threads:[~2006-11-29 14:50 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-29 14:50 Thiemo Seufer [this message]
2006-11-29 22:06 ` [Qemu-devel] [PATCH 6/6, UPDATE] A cumulative MIPS patchset Paul Brook
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