From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 6/6, UPDATE] A cumulative MIPS patchset
Date: Wed, 29 Nov 2006 22:06:57 +0000 [thread overview]
Message-ID: <200611292206.59417.paul@codesourcery.com> (raw)
In-Reply-To: <20061129145041.GA2777@networkno.de>
> The emulated CPU still identifies itself as a MIPS32(R1) 4Kc.
> Currently it doesn't throw a RI exception for R2 instructions, this
> is useful for Linux userland emulation, and also follows the current
> policy which doesn't distinguish between MIPS32R1 instructions and
> those of earlier ISAs.
I thought this was an accident/omission rather than a policy.
I recommend making the ISA features optional, even it it's controlled by a
compile-time directive that's always on. It's much easier to do this when
adding the insns then to retro-fit it afterwards.
Paul
prev parent reply other threads:[~2006-11-29 22:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-29 14:50 [Qemu-devel] [PATCH 6/6, UPDATE] A cumulative MIPS patchset Thiemo Seufer
2006-11-29 22:06 ` Paul Brook [this message]
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