From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GxMLp-0003OH-VP for qemu-devel@nongnu.org; Thu, 21 Dec 2006 06:44:42 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GxMLn-0003O5-Ul for qemu-devel@nongnu.org; Thu, 21 Dec 2006 06:44:41 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GxMLn-0003O2-Ps for qemu-devel@nongnu.org; Thu, 21 Dec 2006 06:44:39 -0500 Received: from [193.7.176.60] (helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GxMLm-0008PV-R9 for qemu-devel@nongnu.org; Thu, 21 Dec 2006 06:44:39 -0500 Date: Thu, 21 Dec 2006 11:32:34 +0000 From: Thiemo Seufer Subject: Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip... Message-ID: <20061221113234.GA30873@networkno.de> References: <458A57B6.3080901@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <458A57B6.3080901@bellard.org> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabrice Bellard Cc: qemu-devel@nongnu.org Fabrice Bellard wrote: > You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t' > cast... Then it may not work. A MIPS64 CPU requires properly sign-extended 32bit values. Host architectures can define either sign- or zero- Extension for 32bit values in 64bit Registers. Thiemo