From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1H6y6y-0006OX-Mk for qemu-devel@nongnu.org; Tue, 16 Jan 2007 18:53:04 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1H6y6u-0006Nw-Ck for qemu-devel@nongnu.org; Tue, 16 Jan 2007 18:53:04 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1H6y6u-0006Nt-7a for qemu-devel@nongnu.org; Tue, 16 Jan 2007 18:53:00 -0500 Received: from [82.232.2.251] (helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1H6y6t-0000I7-Pw for qemu-devel@nongnu.org; Tue, 16 Jan 2007 18:53:00 -0500 Received: from amd64.aurel32.net ([2001:618:400:fc13:216:3eff:fe00:1009]) by mail.aurel32.net with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1H6y6u-0002m7-Ku for qemu-devel@nongnu.org; Wed, 17 Jan 2007 00:53:00 +0100 Received: from aurel32 by amd64.aurel32.net with local (Exim 4.63) (envelope-from ) id 1H6y6u-00067M-Dx for qemu-devel@nongnu.org; Wed, 17 Jan 2007 00:53:00 +0100 Date: Wed, 17 Jan 2007 00:53:00 +0100 From: Aurelien Jarno Message-ID: <20070116235300.GA23509@amd64.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Subject: [Qemu-devel] [PATCH] GT64120 big-endian fix Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The patch below (partly) fixes the big-endian support for the GT64120 northbridge. This is the correct way to implement byte swapping, but this chip also allow byte swapping on the PCI bus depending on a configuration bit. This is not yet implemented, but also not used by the Linux kernel. This patch also adds support for a few more registers. Index: hw/gt64xxx.c =================================================================== RCS file: /sources/qemu/qemu/hw/gt64xxx.c,v retrieving revision 1.1 diff -u -d -p -r1.1 gt64xxx.c --- hw/gt64xxx.c 15 Jan 2007 18:32:02 -0000 1.1 +++ hw/gt64xxx.c 16 Jan 2007 23:36:44 -0000 @@ -240,14 +240,19 @@ static void gt64120_writel (void *opaque GT64120State *s = opaque; uint32_t saddr; +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap32(val); +#endif + saddr = (addr & 0xfff) >> 2; switch (saddr) { - /* CPU Configuration Register */ + + /* CPU Configuration */ case GT_CPU: s->regs[GT_CPU] = val; - gt64120_pci_mapping(s); break; case GT_MULTI: + /* Read-only register as only one GT64xxx is present on the CPU bus */ break; /* CPU Address Decode */ @@ -306,6 +311,13 @@ static void gt64120_writel (void *opaque case GT_CPUERR_DATALO: case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: + /* Read-only registers, do nothing */ + break; + + /* CPU Sync Barrier */ + case GT_PCI0SYNC: + case GT_PCI1SYNC: + /* Read-only registers, do nothing */ break; /* ECC */ @@ -314,6 +326,7 @@ static void gt64120_writel (void *opaque case GT_ECC_MEM: case GT_ECC_CALC: case GT_ECC_ERRADDR: + /* Read-only registers, do nothing */ break; /* PCI Internal */ @@ -328,6 +341,16 @@ static void gt64120_writel (void *opaque pci_host_data_writel(s->pci, 0, val); break; + /* SDRAM Parameters */ + case GT_SDRAM_B0: + case GT_SDRAM_B1: + case GT_SDRAM_B2: + case GT_SDRAM_B3: + /* We don't simulate electrical parameters of the SDRAM. + Accept, but ignore the values. */ + s->regs[saddr] = val; + break; + default: #if 0 printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr); @@ -348,13 +371,31 @@ static uint32_t gt64120_readl (void *opa switch (saddr) { + /* CPU Configuration */ + case GT_MULTI: + /* Only one GT64xxx is present on the CPU bus, return + the initial value */ + val = s->regs[saddr]; + break; + /* CPU Error Report */ case GT_CPUERR_ADDRLO: case GT_CPUERR_ADDRHI: case GT_CPUERR_DATALO: case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: - return 0; + /* Emulated memory has no error, always return the initial + values */ + val = s->regs[saddr]; + break; + + /* CPU Sync Barrier */ + case GT_PCI0SYNC: + case GT_PCI1SYNC: + /* Reading those register should empty all FIFO on the PCI + bus, which are not emulated. The return value should be + a random value that should be ignored. */ + val = 0xc000ffee; break; /* ECC */ @@ -363,11 +404,12 @@ static uint32_t gt64120_readl (void *opa case GT_ECC_MEM: case GT_ECC_CALC: case GT_ECC_ERRADDR: - return 0; + /* Emulated memory has no error, always return the initial + values */ + val = s->regs[saddr]; break; case GT_CPU: - case GT_MULTI: case GT_PCI0IOLD: case GT_PCI0M0LD: case GT_PCI0M1LD: @@ -394,6 +436,16 @@ static uint32_t gt64120_readl (void *opa val = pic_intack_read(isa_pic); break; + /* SDRAM Parameters */ + case GT_SDRAM_B0: + case GT_SDRAM_B1: + case GT_SDRAM_B2: + case GT_SDRAM_B3: + /* We don't simulate electrical parameters of the SDRAM. + Just return the last written value. */ + val = s->regs[saddr]; + break; + /* PCI Internal */ case GT_PCI0_CFGADDR: val = s->pci->config_reg; @@ -410,7 +462,11 @@ static uint32_t gt64120_readl (void *opa break; } +#ifdef TARGET_WORDS_BIGENDIAN + return bswap32(val); +#else return val; +#endif } static CPUWriteMemoryFunc *gt64120_write[] = { @@ -521,6 +577,12 @@ void gt64120_reset(void *opaque) s->regs[GT_ECC_CALC] = 0x00000000; s->regs[GT_ECC_ERRADDR] = 0x00000000; + /* SDRAM Parameters */ + s->regs[GT_SDRAM_B0] = 0x00000005; + s->regs[GT_SDRAM_B1] = 0x00000005; + s->regs[GT_SDRAM_B2] = 0x00000005; + s->regs[GT_SDRAM_B3] = 0x00000005; + /* PCI Internal FIXME: not complete*/ #ifdef TARGET_WORDS_BIGENDIAN s->regs[GT_PCI0_CMD] = 0x00000000; -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net