[Qemu-devel] [RFC] IRQ acknowledge on MIPS

[Aurelien Jarno <aurelien@aurel32.net>]

Hi all,

There is currently a bug concerning the IRQ acknowlege on the MIPS
system emulation. It concerns both the QEMU and Malta boards, though it
is only detectable with a 2.4 kernel and thus on the Malta board. The
symptom is a storm of "We got a spurious interrupt from PIIX4."

This is due to the kernel requesting the interrupt number from the 
i8259A where no interrupt is waiting. In such a case the i8259A answers
by an IRQ 7.

When an hardware interrupt occurs, the i8259A memorizes the interrupt
and sends it to the MIPS CPU. This is done via the pic_irq_request()
function. The result is that the bit 10 of the CP0 Cause register is 
set to one (interrupt 2). But when the interrupt is finished, the i8259a
registers IRR and ISR are cleared, but not the CP0 Cause register. The
CPU always thinks there is an interrupt to serve, which is wrong.

The patch below addresses the problem, but it is just a way to show the
problem and the fix. It is not clean to merge it, except the GT64120
part.

With this patch the problem is fixed, and I see a 12% improvement in
the boot time of a Debian system.

Does anyone has an idea of a sane implementation for that? It seems
only the MIPS platform has to clear a register of the CPU when an
interrupt is finished.

Thanks,
Aurelien



Index: gt64xxx.c
===================================================================
RCS file: /sources/qemu/qemu/hw/gt64xxx.c,v
retrieving revision 1.2
diff -u -d -p -r1.2 gt64xxx.c
--- gt64xxx.c	17 Jan 2007 23:35:01 -0000	1.2
+++ gt64xxx.c	23 Jan 2007 00:34:14 -0000
@@ -433,7 +436,8 @@ static uint32_t gt64120_readl (void *opa
         val = s->regs[saddr];
         break;
     case GT_PCI0_IACK:
- 	val = pic_intack_read(isa_pic);
+        /* Read the IRQ number */ 
+        val = pic_read_irq(isa_pic);
         break;
 
     /* SDRAM Parameters */
Index: i8259.c
===================================================================
RCS file: /sources/qemu/qemu/hw/i8259.c,v
retrieving revision 1.19
diff -u -d -p -r1.19 i8259.c
--- i8259.c	25 Jun 2006 18:15:31 -0000	1.19
+++ i8259.c	23 Jan 2007 00:34:15 -0000
@@ -161,6 +161,8 @@ void pic_update_irq(PicState2 *s)
 #endif
         s->irq_request(s->irq_request_opaque, 1);
     }
+    else
+        s->irq_request(s->irq_request_opaque, 0);
 }
 
 #ifdef DEBUG_IRQ_LATENCY
Index: mips_malta.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.4
diff -u -d -p -r1.4 mips_malta.c
--- mips_malta.c	20 Jan 2007 00:29:01 -0000	1.4
+++ mips_malta.c	23 Jan 2007 00:34:15 -0000
@@ -62,7 +62,7 @@ static void pic_irq_request(void *opaque
         cpu_interrupt(env, CPU_INTERRUPT_HARD);
     } else {
 	env->CP0_Cause &= ~0x00000400;
-        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        /* cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); */
     }
 }
 
Index: mips_r4k.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_r4k.c,v
retrieving revision 1.31
diff -u -d -p -r1.31 mips_r4k.c
--- mips_r4k.c	6 Jan 2007 02:24:15 -0000	1.31
+++ mips_r4k.c	23 Jan 2007 00:34:15 -0000
@@ -44,7 +44,7 @@ static void pic_irq_request(void *opaque
         cpu_interrupt(env, CPU_INTERRUPT_HARD);
     } else {
 	env->CP0_Cause &= ~0x00000400;
-        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        /* cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); */
     }
 }
 

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net