From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1H9Nlu-0006eo-Cv for qemu-devel@nongnu.org; Tue, 23 Jan 2007 10:41:18 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1H9Nls-0006b9-Rb for qemu-devel@nongnu.org; Tue, 23 Jan 2007 10:41:18 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1H9Nls-0006ax-OH for qemu-devel@nongnu.org; Tue, 23 Jan 2007 10:41:16 -0500 Received: from [65.74.133.4] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1H9Nls-0003Kf-7B for qemu-devel@nongnu.org; Tue, 23 Jan 2007 10:41:16 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [RFC] IRQ acknowledge on MIPS Date: Tue, 23 Jan 2007 15:40:51 +0000 References: <20070123004819.GA10927@amd64.aurel32.net> <45B5CED0.7020807@aurel32.net> <00f801c73f03$0b552650$e90d11ac@spb.in.rosprint.ru> In-Reply-To: <00f801c73f03$0b552650$e90d11ac@spb.in.rosprint.ru> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200701231540.52240.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Alexander Voropay > It should be good to have a well-defined modular IRQ routing > architecture in the Qemu. We've got most of one for the ARM targets (see hw/arm_pic.h). This file contains both the target independent bits and the ARM specific bits for emulating the CPU IRQ/FIQ pins. Annother possibility to abstract this to use a single interrupt line object rather than an {object,index} pair. This simplifies code that that raises interrupts, at the expense of some complication in the code to create interrupt controllers. Paul