* [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
@ 2007-01-23 21:26 Ed Swierk
2007-01-23 21:49 ` Fabrice Bellard
0 siblings, 1 reply; 8+ messages in thread
From: Ed Swierk @ 2007-01-23 21:26 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 677 bytes --]
The attached patch adds SMBus host support to the emulated PIIX4 power
management device (acpi.c), and adds an emulated serial EEPROM device
accessible via the SMBus interface.
I tried to follow the Intel 82371AB spec for the SMBus support; the
interface should be generic enough to implement a variety of
SMBus-compliant devices.
The EEPROM device can use a file for persistent storage
(smbus_eeprom.bin in the BIOS directory). If this file does not exist,
a temporary buffer is used instead.
I tested the devices with Linux using the i2c-piix4 host driver and
the eeprom chip driver. I have no idea what will happen on other OSes.
Comments and suggestions welcome.
--Ed
[-- Attachment #2: qemu-piix4-smbus-eeprom.patch --]
[-- Type: text/x-patch, Size: 13967 bytes --]
Index: qemu-0.8.2/hw/acpi.c
===================================================================
--- qemu-0.8.2.orig/hw/acpi.c
+++ qemu-0.8.2/hw/acpi.c
@@ -27,6 +27,7 @@
#define PM_IO_BASE 0xb000
#define SMI_CMD_IO_ADDR 0xb040
#define ACPI_DBG_IO_ADDR 0xb044
+#define SMB_IO_BASE 0xb100
typedef struct PIIX4PMState {
PCIDevice dev;
@@ -35,6 +36,15 @@ typedef struct PIIX4PMState {
uint16_t pmcntrl;
QEMUTimer *tmr_timer;
int64_t tmr_overflow_time;
+ SMBusDevice *smb_dev[128];
+ uint8_t smb_stat;
+ uint8_t smb_ctl;
+ uint8_t smb_cmd;
+ uint8_t smb_addr;
+ uint8_t smb_data0;
+ uint8_t smb_data1;
+ uint8_t smb_data[32];
+ uint8_t smb_index;
} PIIX4PMState;
#define RTC_EN (1 << 10)
@@ -46,8 +56,6 @@ typedef struct PIIX4PMState {
#define SUS_EN (1 << 13)
-/* Note: only used for ACPI bios init. Could be deleted when ACPI init
- is integrated in Bochs BIOS */
static PIIX4PMState *piix4_pm_state;
static uint32_t get_pmtmr(PIIX4PMState *s)
@@ -218,13 +226,163 @@ static void acpi_dbg_writel(void *opaque
#endif
}
+static void smb_transaction(PIIX4PMState *s)
+{
+ uint8_t prot = (s->smb_ctl >> 2) & 0x07;
+ uint8_t read = s->smb_addr & 0x01;
+ uint8_t cmd = s->smb_cmd;
+ uint8_t addr = s->smb_addr >> 1;
+ SMBusDevice *dev = s->smb_dev[addr];
+
+#ifdef DEBUG
+ printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+#endif
+ if (!dev) goto error;
+
+ switch(prot) {
+ case 0x0:
+ if (!dev->quick_cmd) goto error;
+ (*dev->quick_cmd)(dev, read);
+ break;
+ case 0x1:
+ if (read) {
+ if (!dev->receive_byte) goto error;
+ s->smb_data0 = (*dev->receive_byte)(dev);
+ }
+ else {
+ if (!dev->send_byte) goto error;
+ (*dev->send_byte)(dev, cmd);
+ }
+ break;
+ case 0x2:
+ if (read) {
+ if (!dev->read_byte) goto error;
+ s->smb_data0 = (*dev->read_byte)(dev, cmd);
+ }
+ else {
+ if (!dev->write_byte) goto error;
+ (*dev->write_byte)(dev, cmd, s->smb_data0);
+ }
+ break;
+ case 0x3:
+ if (read) {
+ uint16_t val;
+ if (!dev->read_word) goto error;
+ val = (*dev->read_word)(dev, cmd);
+ s->smb_data0 = val;
+ s->smb_data1 = val >> 8;
+ }
+ else {
+ if (!dev->write_word) goto error;
+ (*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
+ }
+ break;
+ case 0x5:
+ if (read) {
+ if (!dev->read_block) goto error;
+ s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
+ }
+ else {
+ if (!dev->write_block) goto error;
+ (*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
+ }
+ break;
+ default:
+ goto error;
+ }
+ return;
+
+ error:
+ s->smb_stat |= 0x04;
+}
+
+static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ PIIX4PMState *s = opaque;
+ addr &= 0x3f;
+#ifdef DEBUG
+ printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ switch(addr) {
+ case 0x00: /* SMBHSTSTS */
+ s->smb_stat = 0;
+ s->smb_index = 0;
+ break;
+ case 0x02: /* SMBHSTCNT */
+ s->smb_ctl = val;
+ if (val & 0x40)
+ smb_transaction(s);
+ break;
+ case 0x03: /* SMBHSTCMD */
+ s->smb_cmd = val;
+ break;
+ case 0x04: /* SMBHSTADD */
+ s->smb_addr = val;
+ break;
+ case 0x05: /* SMBHSTDAT0 */
+ s->smb_data0 = val;
+ break;
+ case 0x06: /* SMBHSTDAT1 */
+ s->smb_data1 = val;
+ break;
+ case 0x07: /* SMBBLKDAT */
+ s->smb_data[s->smb_index++] = val;
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ PIIX4PMState *s = opaque;
+ uint32_t val;
+
+ addr &= 0x3f;
+ switch(addr) {
+ case 0x00: /* SMBHSTSTS */
+ val = s->smb_stat;
+ break;
+ case 0x02: /* SMBHSTCNT */
+ s->smb_index = 0;
+ val = s->smb_ctl & 0x1f;
+ break;
+ case 0x03: /* SMBHSTCMD */
+ val = s->smb_cmd;
+ break;
+ case 0x04: /* SMBHSTADD */
+ val = s->smb_addr;
+ break;
+ case 0x05: /* SMBHSTDAT0 */
+ val = s->smb_data0;
+ break;
+ case 0x06: /* SMBHSTDAT1 */
+ val = s->smb_data1;
+ break;
+ case 0x07: /* SMBBLKDAT */
+ val = s->smb_data[s->smb_index++];
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ val = 0;
+ break;
+ }
+#ifdef DEBUG
+ printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ return val;
+}
+
/* XXX: we still add it to the PIIX3 and we count on the fact that
OSes are smart enough to accept this strange configuration */
void piix4_pm_init(PCIBus *bus, int devfn)
{
PIIX4PMState *s;
uint8_t *pci_conf;
- uint32_t pm_io_base;
+ uint32_t pm_io_base, smb_io_base;
s = (PIIX4PMState *)pci_register_device(bus,
"PM", sizeof(PIIX4PMState),
@@ -259,10 +417,22 @@ void piix4_pm_init(PCIBus *bus, int devf
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
(serial_hds[1] != NULL ? 0x90 : 0);
+ smb_io_base = SMB_IO_BASE;
+ pci_conf[0x90] = smb_io_base | 1;
+ pci_conf[0x91] = smb_io_base >> 8;
+ pci_conf[0xd2] = 0x09;
+ register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
+ register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
+
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
piix4_pm_state = s;
}
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
+{
+ piix4_pm_state->smb_dev[addr] = dev;
+}
+
/* ACPI tables */
/* XXX: move them in the Bochs BIOS ? */
Index: qemu-0.8.2/hw/smbus.h
===================================================================
--- /dev/null
+++ qemu-0.8.2/hw/smbus.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU SMBus API
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct SMBusDevice SMBusDevice;
+
+struct SMBusDevice {
+ uint8_t addr;
+ void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
+ void (*send_byte)(SMBusDevice *dev, uint8_t val);
+ uint8_t (*receive_byte)(SMBusDevice *dev);
+ void (*write_byte)(SMBusDevice *dev, uint8_t cmd, uint8_t val);
+ uint8_t (*read_byte)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_word)(SMBusDevice *dev, uint8_t cmd, uint16_t val);
+ uint16_t (*read_word)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_block)(SMBusDevice *dev, uint8_t cmd, uint8_t len, uint8_t *buf);
+ uint8_t (*read_block)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf);
+};
Index: qemu-0.8.2/hw/smbus_eeprom.c
===================================================================
--- /dev/null
+++ qemu-0.8.2/hw/smbus_eeprom.c
@@ -0,0 +1,94 @@
+/*
+ * QEMU SMBus EEPROM device
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "vl.h"
+
+//#define DEBUG
+
+typedef struct SMBusEEPROMDevice {
+ SMBusDevice dev;
+ uint8_t *data;
+ uint8_t offset;
+} SMBusEEPROMDevice;
+
+static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read)
+{
+#ifdef DEBUG
+ printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->addr, read);
+#endif
+}
+
+static void eeprom_send_byte(SMBusDevice *dev, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_send_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ eeprom->offset = val;
+}
+
+static uint8_t eeprom_receive_byte(SMBusDevice *dev)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[eeprom->offset++];
+#ifdef DEBUG
+ printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ return val;
+}
+
+static void eeprom_write_byte(SMBusDevice *dev, uint8_t cmd, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ eeprom->data[cmd] = val;
+}
+
+static uint8_t eeprom_read_byte(SMBusDevice *dev, uint8_t cmd)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[cmd];
+#ifdef DEBUG
+ printf("eeprom_read_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ return val;
+}
+
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf)
+{
+ SMBusEEPROMDevice *eeprom = qemu_mallocz(sizeof(SMBusEEPROMDevice));
+ eeprom->dev.addr = addr;
+ eeprom->dev.quick_cmd = eeprom_quick_cmd;
+ eeprom->dev.send_byte = eeprom_send_byte;
+ eeprom->dev.receive_byte = eeprom_receive_byte;
+ eeprom->dev.write_byte = eeprom_write_byte;
+ eeprom->dev.read_byte = eeprom_read_byte;
+ eeprom->data = buf;
+ eeprom->offset = 0;
+ return (SMBusDevice *) eeprom;
+}
Index: qemu-0.8.2/vl.h
===================================================================
--- qemu-0.8.2.orig/vl.h
+++ qemu-0.8.2/vl.h
@@ -917,11 +917,17 @@ int pit_get_out(PITState *pit, int chann
void pcspk_init(PITState *);
int pcspk_audio_init(AudioState *);
+#include "hw/smbus.h"
+
/* acpi.c */
extern int acpi_enabled;
void piix4_pm_init(PCIBus *bus, int devfn);
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
void acpi_bios_init(void);
+/* smbus_eeprom.c */
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
+
/* pc.c */
extern QEMUMachine pc_machine;
extern QEMUMachine isapc_machine;
Index: qemu-0.8.2/hw/pc.c
===================================================================
--- qemu-0.8.2.orig/hw/pc.c
+++ qemu-0.8.2/hw/pc.c
@@ -24,6 +24,7 @@
#include "vl.h"
#include <dlfcn.h> /* For dlopen of hw plugin shared libraries */
+#include <sys/mman.h>
/* output Bochs bios info messages */
//#define DEBUG_BIOS
@@ -32,6 +33,7 @@
#define VGABIOS_FILENAME "vgabios.bin"
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
#define LINUX_BOOT_FILENAME "linux_boot.bin"
+#define SMBUS_EEPROM_FILENAME "smbus_eeprom.bin"
#define KERNEL_LOAD_ADDR 0x00100000
#define INITRD_LOAD_ADDR 0x00600000
@@ -863,7 +865,22 @@ static void pc_init1(int ram_size, int v
}
if (pci_enabled && acpi_enabled) {
+ int f;
+ uint8_t *d = MAP_FAILED;
piix4_pm_init(pci_bus, piix3_devfn + 3);
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, SMBUS_EEPROM_FILENAME);
+ f = open(buf, O_RDWR);
+ if (f >= 0) {
+ ftruncate(f, 8 * 256);
+ d = mmap(0, 8 * 256, PROT_READ | PROT_WRITE, MAP_SHARED, f, 0);
+ }
+ if (d == MAP_FAILED)
+ d = qemu_mallocz(8 * 256);
+ for (i = 0; i < 8; i++) {
+ SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i,
+ d + (i * 256));
+ piix4_smbus_register_device(eeprom, 0x50 + i);
+ }
}
#if 0
Index: qemu-0.8.2/Makefile.target
===================================================================
--- qemu-0.8.2.orig/Makefile.target
+++ qemu-0.8.2/Makefile.target
@@ -338,7 +338,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o piix_pci.o
-VL_OBJS+= usb-uhci.o
+VL_OBJS+= usb-uhci.o smbus_eeprom.o
DEFINES += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), ppc)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 21:26 [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation Ed Swierk
@ 2007-01-23 21:49 ` Fabrice Bellard
2007-01-23 22:30 ` Ed Swierk
2007-01-23 23:22 ` Ed Swierk
0 siblings, 2 replies; 8+ messages in thread
From: Fabrice Bellard @ 2007-01-23 21:49 UTC (permalink / raw)
To: qemu-devel
Ed Swierk wrote:
> The attached patch adds SMBus host support to the emulated PIIX4 power
> management device (acpi.c), and adds an emulated serial EEPROM device
> accessible via the SMBus interface.
>
> I tried to follow the Intel 82371AB spec for the SMBus support; the
> interface should be generic enough to implement a variety of
> SMBus-compliant devices.
>
> The EEPROM device can use a file for persistent storage
> (smbus_eeprom.bin in the BIOS directory). If this file does not exist,
> a temporary buffer is used instead.
>
> I tested the devices with Linux using the i2c-piix4 host driver and
> the eeprom chip driver. I have no idea what will happen on other OSes.
>
> Comments and suggestions welcome.
> [...]
OK, but avoid using mmap() in the device code. Moreover, files in the
BIOS directory are not writable.
Regards,
Fabrice.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 21:49 ` Fabrice Bellard
@ 2007-01-23 22:30 ` Ed Swierk
2007-01-23 23:22 ` Ed Swierk
1 sibling, 0 replies; 8+ messages in thread
From: Ed Swierk @ 2007-01-23 22:30 UTC (permalink / raw)
To: qemu-devel
On 1/23/07, Fabrice Bellard <fabrice@bellard.org> wrote:
> OK, but avoid using mmap() in the device code. Moreover, files in the
> BIOS directory are not writable.
OK. Would it be better to do the following:
- add a command-line option -seeprom that sets the file to use as
backing store for the smbus_eeprom device
- in main(), open and mmap the file if the -seeprom option is
specified, otherwise allocate a temporary buffer
- add a seeprom buffer argument to each machine's init(), ignored except for pc
--Ed
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 21:49 ` Fabrice Bellard
2007-01-23 22:30 ` Ed Swierk
@ 2007-01-23 23:22 ` Ed Swierk
2007-01-24 1:55 ` Ed Swierk
` (2 more replies)
1 sibling, 3 replies; 8+ messages in thread
From: Ed Swierk @ 2007-01-23 23:22 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 192 bytes --]
Here's a revised patch with the mmap stuff removed. I'll refine the
persistence support, but in the meantime the EEPROM device is usable
even if it forgets its contents when qemu exits.
--Ed
[-- Attachment #2: qemu-piix4-smbus-eeprom.patch --]
[-- Type: text/x-patch, Size: 13202 bytes --]
Index: qemu-0.8.2/hw/acpi.c
===================================================================
--- qemu-0.8.2.orig/hw/acpi.c
+++ qemu-0.8.2/hw/acpi.c
@@ -27,6 +27,7 @@
#define PM_IO_BASE 0xb000
#define SMI_CMD_IO_ADDR 0xb040
#define ACPI_DBG_IO_ADDR 0xb044
+#define SMB_IO_BASE 0xb100
typedef struct PIIX4PMState {
PCIDevice dev;
@@ -35,6 +36,15 @@ typedef struct PIIX4PMState {
uint16_t pmcntrl;
QEMUTimer *tmr_timer;
int64_t tmr_overflow_time;
+ SMBusDevice *smb_dev[128];
+ uint8_t smb_stat;
+ uint8_t smb_ctl;
+ uint8_t smb_cmd;
+ uint8_t smb_addr;
+ uint8_t smb_data0;
+ uint8_t smb_data1;
+ uint8_t smb_data[32];
+ uint8_t smb_index;
} PIIX4PMState;
#define RTC_EN (1 << 10)
@@ -46,8 +56,6 @@ typedef struct PIIX4PMState {
#define SUS_EN (1 << 13)
-/* Note: only used for ACPI bios init. Could be deleted when ACPI init
- is integrated in Bochs BIOS */
static PIIX4PMState *piix4_pm_state;
static uint32_t get_pmtmr(PIIX4PMState *s)
@@ -218,13 +226,163 @@ static void acpi_dbg_writel(void *opaque
#endif
}
+static void smb_transaction(PIIX4PMState *s)
+{
+ uint8_t prot = (s->smb_ctl >> 2) & 0x07;
+ uint8_t read = s->smb_addr & 0x01;
+ uint8_t cmd = s->smb_cmd;
+ uint8_t addr = s->smb_addr >> 1;
+ SMBusDevice *dev = s->smb_dev[addr];
+
+#ifdef DEBUG
+ printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+#endif
+ if (!dev) goto error;
+
+ switch(prot) {
+ case 0x0:
+ if (!dev->quick_cmd) goto error;
+ (*dev->quick_cmd)(dev, read);
+ break;
+ case 0x1:
+ if (read) {
+ if (!dev->receive_byte) goto error;
+ s->smb_data0 = (*dev->receive_byte)(dev);
+ }
+ else {
+ if (!dev->send_byte) goto error;
+ (*dev->send_byte)(dev, cmd);
+ }
+ break;
+ case 0x2:
+ if (read) {
+ if (!dev->read_byte) goto error;
+ s->smb_data0 = (*dev->read_byte)(dev, cmd);
+ }
+ else {
+ if (!dev->write_byte) goto error;
+ (*dev->write_byte)(dev, cmd, s->smb_data0);
+ }
+ break;
+ case 0x3:
+ if (read) {
+ uint16_t val;
+ if (!dev->read_word) goto error;
+ val = (*dev->read_word)(dev, cmd);
+ s->smb_data0 = val;
+ s->smb_data1 = val >> 8;
+ }
+ else {
+ if (!dev->write_word) goto error;
+ (*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
+ }
+ break;
+ case 0x5:
+ if (read) {
+ if (!dev->read_block) goto error;
+ s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
+ }
+ else {
+ if (!dev->write_block) goto error;
+ (*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
+ }
+ break;
+ default:
+ goto error;
+ }
+ return;
+
+ error:
+ s->smb_stat |= 0x04;
+}
+
+static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ PIIX4PMState *s = opaque;
+ addr &= 0x3f;
+#ifdef DEBUG
+ printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ switch(addr) {
+ case 0x00: /* SMBHSTSTS */
+ s->smb_stat = 0;
+ s->smb_index = 0;
+ break;
+ case 0x02: /* SMBHSTCNT */
+ s->smb_ctl = val;
+ if (val & 0x40)
+ smb_transaction(s);
+ break;
+ case 0x03: /* SMBHSTCMD */
+ s->smb_cmd = val;
+ break;
+ case 0x04: /* SMBHSTADD */
+ s->smb_addr = val;
+ break;
+ case 0x05: /* SMBHSTDAT0 */
+ s->smb_data0 = val;
+ break;
+ case 0x06: /* SMBHSTDAT1 */
+ s->smb_data1 = val;
+ break;
+ case 0x07: /* SMBBLKDAT */
+ s->smb_data[s->smb_index++] = val;
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ PIIX4PMState *s = opaque;
+ uint32_t val;
+
+ addr &= 0x3f;
+ switch(addr) {
+ case 0x00: /* SMBHSTSTS */
+ val = s->smb_stat;
+ break;
+ case 0x02: /* SMBHSTCNT */
+ s->smb_index = 0;
+ val = s->smb_ctl & 0x1f;
+ break;
+ case 0x03: /* SMBHSTCMD */
+ val = s->smb_cmd;
+ break;
+ case 0x04: /* SMBHSTADD */
+ val = s->smb_addr;
+ break;
+ case 0x05: /* SMBHSTDAT0 */
+ val = s->smb_data0;
+ break;
+ case 0x06: /* SMBHSTDAT1 */
+ val = s->smb_data1;
+ break;
+ case 0x07: /* SMBBLKDAT */
+ val = s->smb_data[s->smb_index++];
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ val = 0;
+ break;
+ }
+#ifdef DEBUG
+ printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ return val;
+}
+
/* XXX: we still add it to the PIIX3 and we count on the fact that
OSes are smart enough to accept this strange configuration */
void piix4_pm_init(PCIBus *bus, int devfn)
{
PIIX4PMState *s;
uint8_t *pci_conf;
- uint32_t pm_io_base;
+ uint32_t pm_io_base, smb_io_base;
s = (PIIX4PMState *)pci_register_device(bus,
"PM", sizeof(PIIX4PMState),
@@ -259,10 +417,22 @@ void piix4_pm_init(PCIBus *bus, int devf
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
(serial_hds[1] != NULL ? 0x90 : 0);
+ smb_io_base = SMB_IO_BASE;
+ pci_conf[0x90] = smb_io_base | 1;
+ pci_conf[0x91] = smb_io_base >> 8;
+ pci_conf[0xd2] = 0x09;
+ register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
+ register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
+
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
piix4_pm_state = s;
}
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
+{
+ piix4_pm_state->smb_dev[addr] = dev;
+}
+
/* ACPI tables */
/* XXX: move them in the Bochs BIOS ? */
Index: qemu-0.8.2/hw/smbus.h
===================================================================
--- /dev/null
+++ qemu-0.8.2/hw/smbus.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU SMBus API
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct SMBusDevice SMBusDevice;
+
+struct SMBusDevice {
+ uint8_t addr;
+ void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
+ void (*send_byte)(SMBusDevice *dev, uint8_t val);
+ uint8_t (*receive_byte)(SMBusDevice *dev);
+ void (*write_byte)(SMBusDevice *dev, uint8_t cmd, uint8_t val);
+ uint8_t (*read_byte)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_word)(SMBusDevice *dev, uint8_t cmd, uint16_t val);
+ uint16_t (*read_word)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_block)(SMBusDevice *dev, uint8_t cmd, uint8_t len, uint8_t *buf);
+ uint8_t (*read_block)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf);
+};
Index: qemu-0.8.2/hw/smbus_eeprom.c
===================================================================
--- /dev/null
+++ qemu-0.8.2/hw/smbus_eeprom.c
@@ -0,0 +1,94 @@
+/*
+ * QEMU SMBus EEPROM device
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "vl.h"
+
+//#define DEBUG
+
+typedef struct SMBusEEPROMDevice {
+ SMBusDevice dev;
+ uint8_t *data;
+ uint8_t offset;
+} SMBusEEPROMDevice;
+
+static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read)
+{
+#ifdef DEBUG
+ printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->addr, read);
+#endif
+}
+
+static void eeprom_send_byte(SMBusDevice *dev, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_send_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ eeprom->offset = val;
+}
+
+static uint8_t eeprom_receive_byte(SMBusDevice *dev)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[eeprom->offset++];
+#ifdef DEBUG
+ printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ return val;
+}
+
+static void eeprom_write_byte(SMBusDevice *dev, uint8_t cmd, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ eeprom->data[cmd] = val;
+}
+
+static uint8_t eeprom_read_byte(SMBusDevice *dev, uint8_t cmd)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[cmd];
+#ifdef DEBUG
+ printf("eeprom_read_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ return val;
+}
+
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf)
+{
+ SMBusEEPROMDevice *eeprom = qemu_mallocz(sizeof(SMBusEEPROMDevice));
+ eeprom->dev.addr = addr;
+ eeprom->dev.quick_cmd = eeprom_quick_cmd;
+ eeprom->dev.send_byte = eeprom_send_byte;
+ eeprom->dev.receive_byte = eeprom_receive_byte;
+ eeprom->dev.write_byte = eeprom_write_byte;
+ eeprom->dev.read_byte = eeprom_read_byte;
+ eeprom->data = buf;
+ eeprom->offset = 0;
+ return (SMBusDevice *) eeprom;
+}
Index: qemu-0.8.2/vl.h
===================================================================
--- qemu-0.8.2.orig/vl.h
+++ qemu-0.8.2/vl.h
@@ -917,11 +917,17 @@ int pit_get_out(PITState *pit, int chann
void pcspk_init(PITState *);
int pcspk_audio_init(AudioState *);
+#include "hw/smbus.h"
+
/* acpi.c */
extern int acpi_enabled;
void piix4_pm_init(PCIBus *bus, int devfn);
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
void acpi_bios_init(void);
+/* smbus_eeprom.c */
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
+
/* pc.c */
extern QEMUMachine pc_machine;
extern QEMUMachine isapc_machine;
Index: qemu-0.8.2/hw/pc.c
===================================================================
--- qemu-0.8.2.orig/hw/pc.c
+++ qemu-0.8.2/hw/pc.c
@@ -863,7 +863,13 @@ static void pc_init1(int ram_size, int v
}
if (pci_enabled && acpi_enabled) {
+ uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
piix4_pm_init(pci_bus, piix3_devfn + 3);
+ for (i = 0; i < 8; i++) {
+ SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i,
+ eeprom_buf + (i * 256));
+ piix4_smbus_register_device(eeprom, 0x50 + i);
+ }
}
#if 0
Index: qemu-0.8.2/Makefile.target
===================================================================
--- qemu-0.8.2.orig/Makefile.target
+++ qemu-0.8.2/Makefile.target
@@ -338,7 +338,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o piix_pci.o
-VL_OBJS+= usb-uhci.o
+VL_OBJS+= usb-uhci.o smbus_eeprom.o
DEFINES += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), ppc)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 23:22 ` Ed Swierk
@ 2007-01-24 1:55 ` Ed Swierk
2007-01-24 20:33 ` Fabrice Bellard
2007-01-31 12:07 ` Thiemo Seufer
2 siblings, 0 replies; 8+ messages in thread
From: Ed Swierk @ 2007-01-24 1:55 UTC (permalink / raw)
To: qemu-devel
Windows 2000 boots and PC Wizard 2007 displays the following
information under the Mainboard category:
> SMBus/i2c Bus : Yes
>> General Information
Device : 82371AB/EB/MB PIIX4/E/M Power Management Controller
Revision : 0
Frequency : 16 KHz
Address : 0xB100
>> Device Capabilities (PCI)
I/O Access : Yes
Memory Access : Yes
Bus Master Capable : Yes
Special Cycle Recognition : No
Memory Write & Invalidate : No
VGA Palette Snoop : No
Parity Error Response : No
Cycle Wait : No
System Error Line : No
Fast Back-to-Back : No
Detects Parity Errors : No
User Defined Format : No
PCI 66Mhz Bus Support : No
New Capability List : No
which hopefully means the patch doesn't break anything.
--Ed
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 23:22 ` Ed Swierk
2007-01-24 1:55 ` Ed Swierk
@ 2007-01-24 20:33 ` Fabrice Bellard
2007-01-31 12:07 ` Thiemo Seufer
2 siblings, 0 replies; 8+ messages in thread
From: Fabrice Bellard @ 2007-01-24 20:33 UTC (permalink / raw)
To: qemu-devel
Ed Swierk wrote:
> Here's a revised patch with the mmap stuff removed. I'll refine the
> persistence support, but in the meantime the EEPROM device is usable
> even if it forgets its contents when qemu exits.
The patch is OK now.
Fabrice.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-23 23:22 ` Ed Swierk
2007-01-24 1:55 ` Ed Swierk
2007-01-24 20:33 ` Fabrice Bellard
@ 2007-01-31 12:07 ` Thiemo Seufer
2007-01-31 17:16 ` Ed Swierk
2 siblings, 1 reply; 8+ messages in thread
From: Thiemo Seufer @ 2007-01-31 12:07 UTC (permalink / raw)
To: Ed Swierk; +Cc: qemu-devel
Ed Swierk wrote:
> Here's a revised patch with the mmap stuff removed. I'll refine the
> persistence support, but in the meantime the EEPROM device is usable
> even if it forgets its contents when qemu exits.
It doesn't apply for current CVS. Could you please update the patch?
I would also prefer to have enums instead of raw constants in all those
case statements.
Thiemo
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation
2007-01-31 12:07 ` Thiemo Seufer
@ 2007-01-31 17:16 ` Ed Swierk
0 siblings, 0 replies; 8+ messages in thread
From: Ed Swierk @ 2007-01-31 17:16 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 236 bytes --]
On 1/31/07, Thiemo Seufer <ths@networkno.de> wrote:
> It doesn't apply for current CVS. Could you please update the patch?
> I would also prefer to have enums instead of raw constants in all those
> case statements.
Here you go.
--Ed
[-- Attachment #2: qemu-piix4-smbus-eeprom.patch --]
[-- Type: text/x-patch, Size: 13465 bytes --]
diff -BurN qemu-snapshot-2007-01-22_05.orig/hw/acpi.c qemu-snapshot-2007-01-22_05/hw/acpi.c
--- qemu-snapshot-2007-01-22_05.orig/hw/acpi.c 2006-10-02 11:25:40.000000000 -0700
+++ qemu-snapshot-2007-01-22_05/hw/acpi.c 2007-01-31 08:59:47.000000000 -0800
@@ -24,6 +24,7 @@
#define PM_FREQ 3579545
#define ACPI_DBG_IO_ADDR 0xb044
+#define SMB_IO_BASE 0xb100
typedef struct PIIX4PMState {
PCIDevice dev;
@@ -34,6 +35,15 @@
uint8_t apms;
QEMUTimer *tmr_timer;
int64_t tmr_overflow_time;
+ SMBusDevice *smb_dev[128];
+ uint8_t smb_stat;
+ uint8_t smb_ctl;
+ uint8_t smb_cmd;
+ uint8_t smb_addr;
+ uint8_t smb_data0;
+ uint8_t smb_data1;
+ uint8_t smb_data[32];
+ uint8_t smb_index;
} PIIX4PMState;
#define RTC_EN (1 << 10)
@@ -45,6 +55,17 @@
#define SUS_EN (1 << 13)
+#define SMBHSTSTS 0x00
+#define SMBHSTCNT 0x02
+#define SMBHSTCMD 0x03
+#define SMBHSTADD 0x04
+#define SMBHSTDAT0 0x05
+#define SMBHSTDAT1 0x06
+#define SMBBLKDAT 0x07
+
+/* Note: only used for piix4_smbus_register_device */
+static PIIX4PMState *piix4_pm_state;
+
static uint32_t get_pmtmr(PIIX4PMState *s)
{
uint32_t d;
@@ -231,6 +252,156 @@
#endif
}
+static void smb_transaction(PIIX4PMState *s)
+{
+ uint8_t prot = (s->smb_ctl >> 2) & 0x07;
+ uint8_t read = s->smb_addr & 0x01;
+ uint8_t cmd = s->smb_cmd;
+ uint8_t addr = s->smb_addr >> 1;
+ SMBusDevice *dev = s->smb_dev[addr];
+
+#ifdef DEBUG
+ printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+#endif
+ if (!dev) goto error;
+
+ switch(prot) {
+ case 0x0:
+ if (!dev->quick_cmd) goto error;
+ (*dev->quick_cmd)(dev, read);
+ break;
+ case 0x1:
+ if (read) {
+ if (!dev->receive_byte) goto error;
+ s->smb_data0 = (*dev->receive_byte)(dev);
+ }
+ else {
+ if (!dev->send_byte) goto error;
+ (*dev->send_byte)(dev, cmd);
+ }
+ break;
+ case 0x2:
+ if (read) {
+ if (!dev->read_byte) goto error;
+ s->smb_data0 = (*dev->read_byte)(dev, cmd);
+ }
+ else {
+ if (!dev->write_byte) goto error;
+ (*dev->write_byte)(dev, cmd, s->smb_data0);
+ }
+ break;
+ case 0x3:
+ if (read) {
+ uint16_t val;
+ if (!dev->read_word) goto error;
+ val = (*dev->read_word)(dev, cmd);
+ s->smb_data0 = val;
+ s->smb_data1 = val >> 8;
+ }
+ else {
+ if (!dev->write_word) goto error;
+ (*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
+ }
+ break;
+ case 0x5:
+ if (read) {
+ if (!dev->read_block) goto error;
+ s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
+ }
+ else {
+ if (!dev->write_block) goto error;
+ (*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
+ }
+ break;
+ default:
+ goto error;
+ }
+ return;
+
+ error:
+ s->smb_stat |= 0x04;
+}
+
+static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ PIIX4PMState *s = opaque;
+ addr &= 0x3f;
+#ifdef DEBUG
+ printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ switch(addr) {
+ case SMBHSTSTS:
+ s->smb_stat = 0;
+ s->smb_index = 0;
+ break;
+ case SMBHSTCNT:
+ s->smb_ctl = val;
+ if (val & 0x40)
+ smb_transaction(s);
+ break;
+ case SMBHSTCMD:
+ s->smb_cmd = val;
+ break;
+ case SMBHSTADD:
+ s->smb_addr = val;
+ break;
+ case SMBHSTDAT0:
+ s->smb_data0 = val;
+ break;
+ case SMBHSTDAT1:
+ s->smb_data1 = val;
+ break;
+ case SMBBLKDAT:
+ s->smb_data[s->smb_index++] = val;
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ PIIX4PMState *s = opaque;
+ uint32_t val;
+
+ addr &= 0x3f;
+ switch(addr) {
+ case SMBHSTSTS:
+ val = s->smb_stat;
+ break;
+ case SMBHSTCNT:
+ s->smb_index = 0;
+ val = s->smb_ctl & 0x1f;
+ break;
+ case SMBHSTCMD:
+ val = s->smb_cmd;
+ break;
+ case SMBHSTADD:
+ val = s->smb_addr;
+ break;
+ case SMBHSTDAT0:
+ val = s->smb_data0;
+ break;
+ case SMBHSTDAT1:
+ val = s->smb_data1;
+ break;
+ case SMBBLKDAT:
+ val = s->smb_data[s->smb_index++];
+ if (s->smb_index > 31)
+ s->smb_index = 0;
+ break;
+ default:
+ val = 0;
+ break;
+ }
+#ifdef DEBUG
+ printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+ return val;
+}
+
static void pm_io_space_update(PIIX4PMState *s)
{
uint32_t pm_io_base;
@@ -302,6 +473,7 @@
{
PIIX4PMState *s;
uint8_t *pci_conf;
+ uint32_t pm_io_base, smb_io_base;
s = (PIIX4PMState *)pci_register_device(bus,
"PM", sizeof(PIIX4PMState),
@@ -332,7 +504,20 @@
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
(serial_hds[1] != NULL ? 0x90 : 0);
+ smb_io_base = SMB_IO_BASE;
+ pci_conf[0x90] = smb_io_base | 1;
+ pci_conf[0x91] = smb_io_base >> 8;
+ pci_conf[0xd2] = 0x09;
+ register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
+ register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
+
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
+ piix4_pm_state = s;
+}
+
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
+{
+ piix4_pm_state->smb_dev[addr] = dev;
}
diff -BurN qemu-snapshot-2007-01-22_05.orig/hw/pc.c qemu-snapshot-2007-01-22_05/hw/pc.c
--- qemu-snapshot-2007-01-22_05.orig/hw/pc.c 2007-01-10 08:23:41.000000000 -0800
+++ qemu-snapshot-2007-01-22_05/hw/pc.c 2007-01-31 08:51:04.000000000 -0800
@@ -699,7 +699,13 @@
}
if (pci_enabled && acpi_enabled) {
+ uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
piix4_pm_init(pci_bus, piix3_devfn + 3);
+ for (i = 0; i < 8; i++) {
+ SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i,
+ eeprom_buf + (i * 256));
+ piix4_smbus_register_device(eeprom, 0x50 + i);
+ }
}
if (i440fx_state) {
diff -BurN qemu-snapshot-2007-01-22_05.orig/hw/smbus_eeprom.c qemu-snapshot-2007-01-22_05/hw/smbus_eeprom.c
--- qemu-snapshot-2007-01-22_05.orig/hw/smbus_eeprom.c 1969-12-31 16:00:00.000000000 -0800
+++ qemu-snapshot-2007-01-22_05/hw/smbus_eeprom.c 2007-01-31 08:51:04.000000000 -0800
@@ -0,0 +1,94 @@
+/*
+ * QEMU SMBus EEPROM device
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "vl.h"
+
+//#define DEBUG
+
+typedef struct SMBusEEPROMDevice {
+ SMBusDevice dev;
+ uint8_t *data;
+ uint8_t offset;
+} SMBusEEPROMDevice;
+
+static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read)
+{
+#ifdef DEBUG
+ printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->addr, read);
+#endif
+}
+
+static void eeprom_send_byte(SMBusDevice *dev, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_send_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ eeprom->offset = val;
+}
+
+static uint8_t eeprom_receive_byte(SMBusDevice *dev)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[eeprom->offset++];
+#ifdef DEBUG
+ printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
+#endif
+ return val;
+}
+
+static void eeprom_write_byte(SMBusDevice *dev, uint8_t cmd, uint8_t val)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+#ifdef DEBUG
+ printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ eeprom->data[cmd] = val;
+}
+
+static uint8_t eeprom_read_byte(SMBusDevice *dev, uint8_t cmd)
+{
+ SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+ uint8_t val = eeprom->data[cmd];
+#ifdef DEBUG
+ printf("eeprom_read_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
+ cmd, val);
+#endif
+ return val;
+}
+
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf)
+{
+ SMBusEEPROMDevice *eeprom = qemu_mallocz(sizeof(SMBusEEPROMDevice));
+ eeprom->dev.addr = addr;
+ eeprom->dev.quick_cmd = eeprom_quick_cmd;
+ eeprom->dev.send_byte = eeprom_send_byte;
+ eeprom->dev.receive_byte = eeprom_receive_byte;
+ eeprom->dev.write_byte = eeprom_write_byte;
+ eeprom->dev.read_byte = eeprom_read_byte;
+ eeprom->data = buf;
+ eeprom->offset = 0;
+ return (SMBusDevice *) eeprom;
+}
diff -BurN qemu-snapshot-2007-01-22_05.orig/hw/smbus.h qemu-snapshot-2007-01-22_05/hw/smbus.h
--- qemu-snapshot-2007-01-22_05.orig/hw/smbus.h 1969-12-31 16:00:00.000000000 -0800
+++ qemu-snapshot-2007-01-22_05/hw/smbus.h 2007-01-31 08:51:04.000000000 -0800
@@ -0,0 +1,38 @@
+/*
+ * QEMU SMBus API
+ *
+ * Copyright (c) 2007 Arastra, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct SMBusDevice SMBusDevice;
+
+struct SMBusDevice {
+ uint8_t addr;
+ void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
+ void (*send_byte)(SMBusDevice *dev, uint8_t val);
+ uint8_t (*receive_byte)(SMBusDevice *dev);
+ void (*write_byte)(SMBusDevice *dev, uint8_t cmd, uint8_t val);
+ uint8_t (*read_byte)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_word)(SMBusDevice *dev, uint8_t cmd, uint16_t val);
+ uint16_t (*read_word)(SMBusDevice *dev, uint8_t cmd);
+ void (*write_block)(SMBusDevice *dev, uint8_t cmd, uint8_t len, uint8_t *buf);
+ uint8_t (*read_block)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf);
+};
diff -BurN qemu-snapshot-2007-01-22_05.orig/Makefile.target qemu-snapshot-2007-01-22_05/Makefile.target
--- qemu-snapshot-2007-01-22_05.orig/Makefile.target 2007-01-21 14:40:04.000000000 -0800
+++ qemu-snapshot-2007-01-22_05/Makefile.target 2007-01-31 09:00:17.000000000 -0800
@@ -365,7 +365,7 @@
VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o piix_pci.o
-VL_OBJS+= usb-uhci.o
+VL_OBJS+= usb-uhci.o smbus_eeprom.o
CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), ppc)
diff -BurN qemu-snapshot-2007-01-22_05.orig/vl.h qemu-snapshot-2007-01-22_05/vl.h
--- qemu-snapshot-2007-01-22_05.orig/vl.h 2007-01-21 08:47:01.000000000 -0800
+++ qemu-snapshot-2007-01-22_05/vl.h 2007-01-31 08:51:04.000000000 -0800
@@ -1043,11 +1043,17 @@
void pcspk_init(PITState *);
int pcspk_audio_init(AudioState *);
+#include "hw/smbus.h"
+
/* acpi.c */
extern int acpi_enabled;
void piix4_pm_init(PCIBus *bus, int devfn);
+void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
void acpi_bios_init(void);
+/* smbus_eeprom.c */
+SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
+
/* pc.c */
extern QEMUMachine pc_machine;
extern QEMUMachine isapc_machine;
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2007-01-31 17:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-01-23 21:26 [Qemu-devel] [PATCH] PIIX4 SMBus host, EEPROM device emulation Ed Swierk
2007-01-23 21:49 ` Fabrice Bellard
2007-01-23 22:30 ` Ed Swierk
2007-01-23 23:22 ` Ed Swierk
2007-01-24 1:55 ` Ed Swierk
2007-01-24 20:33 ` Fabrice Bellard
2007-01-31 12:07 ` Thiemo Seufer
2007-01-31 17:16 ` Ed Swierk
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