From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HOhMa-0003nm-E8 for qemu-devel@nongnu.org; Tue, 06 Mar 2007 16:38:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HOhMY-0003mo-To for qemu-devel@nongnu.org; Tue, 06 Mar 2007 16:38:28 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HOhMY-0003mi-Ir for qemu-devel@nongnu.org; Tue, 06 Mar 2007 16:38:26 -0500 Received: from mx20.gnu.org ([199.232.41.8]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HOhMV-0006VC-Uk for qemu-devel@nongnu.org; Tue, 06 Mar 2007 16:38:24 -0500 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by mx20.gnu.org with esmtp (Exim 4.52) id 1HOh0W-0007kP-VL for qemu-devel@nongnu.org; Tue, 06 Mar 2007 16:15:41 -0500 Date: Tue, 6 Mar 2007 21:05:01 +0000 Subject: Re: [Qemu-devel] [PATCH] Choose emulated MIPS CPU at runtime Message-ID: <20070306210501.GC16210@networkno.de> References: <20070306154919.25DD766CA6@smtp4-g19.free.fr> <20070306173746.GB16210@networkno.de> <45EDBEA0.8070401@mail.berlios.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <45EDBEA0.8070401@mail.berlios.de> From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: qemu-devel@nongnu.org Stefan Weil wrote: > Thiemo Seufer schrieb: > > Looks very nice, except that the CPU models are out of touch with > > reality. :-) > > - There is no CPU called "R4Kc" etc. > > - What Qemu emulates is currently close to a 4KEc with an R3000-style > > FPU attached. (A 4KEc is a 4Kc with MIPS32R2 instructions.) > There exists also an older 4KEc version which only supports > MIPS32R1. AR7 (a SoC from TI) is based on this older version. This can't be correct. 4KEc is defined as a MIPS32R2 core by MIPS Technologies. A MIPS32R1 4KEc would be redundant since that's what the 4Kc is. > I noticed this because some code using DI worked well with QEMU, > but my AR7 based DSL router crashed... Did it die with an RI exception? If not then it sounds more like a missing ehb barrier. Qemu doesn't emulate pipeline hazards... > AR7, it would be nice to switch between MIPS32R1 / MIPS32R2 > instruction sets. It would be nice to see a AR7 router emulation as a separate machine type in Qemu. *hint* *hint* :-) > I think this could be done similar to the FPU > switch, but I don't have a list of the differences, and there are > no MIPS32R2 markers in the QEMU code :-( The specificiation for MIPS{32,64}R{1,2} used to be hidden behind a "free registration" nag screen at http://www.mips.com/ . Unfortunately it isn't ATM, it apparently fell through the cracks of the website relaunch. Thiemo