From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HSGyP-00067Z-Bj for qemu-devel@nongnu.org; Fri, 16 Mar 2007 14:16:17 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HSGyM-00067F-RO for qemu-devel@nongnu.org; Fri, 16 Mar 2007 14:16:16 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HSGyM-00067C-MF for qemu-devel@nongnu.org; Fri, 16 Mar 2007 13:16:14 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HSGxD-000598-Hd for qemu-devel@nongnu.org; Fri, 16 Mar 2007 14:15:03 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Redundant repz prefixes in generated amd64 code Date: Fri, 16 Mar 2007 18:14:57 +0000 References: <200703161415.21283.jseward@acm.org> <200703161428.36897.paul@codesourcery.com> <200703161445.25051.jseward@acm.org> In-Reply-To: <200703161445.25051.jseward@acm.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200703161814.58615.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > > 0000000000008b50 : > > 8b50: 8b 05 00 00 00 00 mov 0(%rip),%eax > > 8b52: R_X86_64_PC32 __op_param1+0x3c > > 8b56: ff e0 jmpq *%rax > > 8b58: f3 c3 repz retq > > > > qemu only strips the final ret off. > > The prefixed ret is to avoid prefetch stalls on amd cpus. > > So the implication of this is that the generated code just happens to > work only because the dangling F3 never ends up in front of some other > instruction which it would change the meaning of? Correct. Paul