From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HSZx7-0007VJ-Db for qemu-devel@nongnu.org; Sat, 17 Mar 2007 10:32:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HSZx6-0007V7-Ac for qemu-devel@nongnu.org; Sat, 17 Mar 2007 10:32:13 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HSZx6-0007V4-7R for qemu-devel@nongnu.org; Sat, 17 Mar 2007 09:32:12 -0500 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HSZvr-0007R1-9i for qemu-devel@nongnu.org; Sat, 17 Mar 2007 10:30:55 -0400 Date: Sat, 17 Mar 2007 14:31:06 +0000 From: Thiemo Seufer Subject: Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction Message-ID: <20070317143106.GF25863@networkno.de> References: <45FB245C.2010900@mail.berlios.de> <20070317004628.GE25863@networkno.de> <45FBD30D.6070403@mail.berlios.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <45FBD30D.6070403@mail.berlios.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: QEMU Developers Stefan Weil wrote: > So an emulation has several options: > > 1. Show undefined behaviour (this is what it does today). > 2. Emulate the behaviour of existing CPUs as far as possible. > As different CPUs behave different, this must depend on the > current CPU. > 3. Display an error message. (3) is bad, as it amounts to a DoS. > The current solution (1) is not good, because users get crashes > and don't know the reason, and experienced users spend a lot of > time with debugging (at least I did). > > Solution (2) is needed to run existing binary code. > > Solution (3) is the minimum I expect of an emulation like QEMU. > > I prefer a mix of solutions (2) and (3): display a message and > try to emulate the original behaviour. > > Do you agree, and would you accept patches which implement this? If the AR7 CPU spec defines the semantics of branch delay slots more precisely than the architecture spec then I'll consider a patch. If this isn't the case then I ask you to use a non-broken compiler/ assembly code. Thiemo