From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HSaTD-0001iY-2Y for qemu-devel@nongnu.org; Sat, 17 Mar 2007 11:05:23 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HSaTB-0001hl-Me for qemu-devel@nongnu.org; Sat, 17 Mar 2007 11:05:22 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HSaTB-0001hg-EY for qemu-devel@nongnu.org; Sat, 17 Mar 2007 10:05:21 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HSaRw-0004HW-69 for qemu-devel@nongnu.org; Sat, 17 Mar 2007 11:04:04 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] PXA-specific ARM hacks. Date: Sat, 17 Mar 2007 15:03:59 +0000 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200703171503.59810.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, balrogg@gmail.com On Friday 16 March 2007 22:06, andrzej zaborowski wrote: > This patch contains some ugly but very useful chnages: > - in cpu-exec.c, halt the arm CPU on CPU_INTERRUPT_HALT like in other > architectures. This is ok. Though I'd prefer it to actually be common code (like CPU_INTERRUPT_DEBUG). > - wake the cpu up on CPU_INTERRUPT_EXITTB - this serves waking the > CPU up without asserting IRQ or FIQ, which is possible on PXA. Would > it be better to add a separate interrupt type instead? I think this is probably ok. Could do with a comment somewhere saying so. > - in target-arm/translate.c, don't terminate the TB after a CP15 > write. The purpose of this is to imitate the real processor's > instruction cache (to some degree). OSes should never need rely on the > cache prefetch but unfortunately Linux for pxa does when it's waking > up from sleep or deep idle, when enabling the MMU (simplifies things a > lot for Linux). This is not acceptable in its current form. IIRC on arm cores the effects take effect once all insn have worked through the pipeline (typically a few cycles), and I bet there's code that relies on this. ie: mcr cp15, ...;nop;nop;nop;nop;@expect cp15 write to have taken effect by now A more acceptable solution would be: - Only extend the TB for the specific instruction that linux abuses - Limit the number of instructions that can follow before the end of the TB. - Add a comment saying what this hack is for. Paul