From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HTb4m-0006J2-SK for qemu-devel@nongnu.org; Tue, 20 Mar 2007 05:56:20 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HTb4k-0006Ie-Pd for qemu-devel@nongnu.org; Tue, 20 Mar 2007 05:56:19 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HTb4k-0006Ib-I0 for qemu-devel@nongnu.org; Tue, 20 Mar 2007 04:56:18 -0500 Received: from phoenix.bawue.net ([193.7.176.60] helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HTb3B-0005oX-Pb for qemu-devel@nongnu.org; Tue, 20 Mar 2007 05:54:41 -0400 Date: Tue, 20 Mar 2007 09:51:50 +0000 From: Thiemo Seufer Subject: Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction Message-ID: <20070320095150.GA2311@networkno.de> References: <20070319223449.GK28895@networkno.de> <054b01c76ac5$0d431470$e90d11ac@spb.in.rosprint.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <054b01c76ac5$0d431470$e90d11ac@spb.in.rosprint.ru> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Voropay Cc: qemu-devel@nongnu.org Alexander Voropay wrote: > "Thiemo Seufer" wrote: > > >For the AR7 case, could you > >- add AR7 as a CPU type > >- handle the interesting cases for AR7 only, after verifying the > > cornercase behaviour of qemu and real hardware is consistent. > > AFAIK, Texas Instrument AR7 isn't a CPU. It's a SoC which > combines well-known MIPS 4KEc synthesizable *core* and ADSL stuff. Other 4KEc behave differently (probably due to differences in the synthesizing technology used), so I figure AR7 becomes a special CPU for qemu's purposes. Thiemo