* [Qemu-devel] [PATCH][SPARC] Tagged add/sub implementation
@ 2007-03-22 22:26 Aurelien Jarno
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From: Aurelien Jarno @ 2007-03-22 22:26 UTC (permalink / raw)
To: qemu-devel
Hi all,
The patch below adds support for taddcc, taddcctv, tsubcc and tsubcctv
that were treated as illegal instructions. With them, the SPARC V8
instruction set is now fully implemented.
Bye,
Aurelien
Index: target-sparc/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.27
diff -u -r1.27 target-sparc/cpu.h
--- target-sparc/cpu.h 31 Jan 2007 12:16:51 -0000 1.27
+++ target-sparc/cpu.h 22 Mar 2007 17:56:27 -0000
@@ -37,6 +37,7 @@
#define TT_WIN_UNF 0x06
#define TT_FP_EXCP 0x08
#define TT_DFAULT 0x09
+#define TT_TOVF 0x0a
#define TT_EXTINT 0x10
#define TT_DIV_ZERO 0x2a
#define TT_TRAP 0x80
@@ -47,6 +48,7 @@
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP 0x21
+#define TT_TOVF 0x23
#define TT_CLRWIN 0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT 0x30
Index: target-sparc/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op.c,v
retrieving revision 1.25
diff -u -r1.25 target-sparc/op.c
--- target-sparc/op.c 19 Mar 2007 19:16:00 -0000 1.25
+++ target-sparc/op.c 22 Mar 2007 17:56:27 -0000
@@ -472,6 +472,96 @@
FORCE_RET();
}
+void OPPROTO op_tadd_T1_T0_cc(void)
+{
+ target_ulong src1;
+
+ src1 = T0;
+ T0 += T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+ if ((src1 & 0x03) || (T1 & 0x03))
+ env->psr |= PSR_OVF;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (T0 < src1)
+ env->xcc |= PSR_CARRY;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+ if ((src1 & 0x03) || (T1 & 0x03))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_tadd_T1_T0_ccTV(void)
+{
+ target_ulong src1;
+
+ if ((T0 & 0x03) || (T1 & 0x03))
+ raise_exception(TT_TOVF);
+
+ src1 = T0;
+ T0 += T1;
+
+#ifdef TARGET_SPARC64
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ raise_exception(TT_TOVF);
+#else
+ if ((src1 & 0x03) || (T1 & 0x03))
+ raise_exception(TT_TOVF);
+#endif
+
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (T0 < src1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+#endif
+ FORCE_RET();
+}
+
void OPPROTO op_sub_T1_T0(void)
{
T0 -= T1;
@@ -582,6 +672,96 @@
FORCE_RET();
}
+void OPPROTO op_tsub_T1_T0_cc(void)
+{
+ target_ulong src1;
+
+ src1 = T0;
+ T0 -= T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+ if ((src1 & 0x03) || (T1 & 0x03))
+ env->psr |= PSR_OVF;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (src1 < T1)
+ env->xcc |= PSR_CARRY;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (src1 < T1)
+ env->psr |= PSR_CARRY;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+ if ((src1 & 0x03) || (T1 & 0x03))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_tsub_T1_T0_ccTV(void)
+{
+ target_ulong src1;
+
+ if ((T0 & 0x03) || (T1 & 0x03))
+ raise_exception(TT_TOVF);
+
+ src1 = T0;
+ T0 -= T1;
+
+#ifdef TARGET_SPARC64
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ raise_exception(TT_TOVF);
+#else
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
+ raise_exception(TT_TOVF);
+#endif
+
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (src1 < T1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (src1 < T1)
+ env->psr |= PSR_CARRY;
+#endif
+ FORCE_RET();
+}
+
void OPPROTO op_and_T1_T0(void)
{
T0 &= T1;
Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v
retrieving revision 1.35
diff -u -r1.35 target-sparc/translate.c
--- target-sparc/translate.c 21 Mar 2007 19:45:50 -0000 1.35
+++ target-sparc/translate.c 22 Mar 2007 17:56:28 -0000
@@ -27,7 +27,6 @@
Optimize synthetic instructions
Optional alignment check
128-bit float
- Tagged add/sub
*/
#include <stdarg.h>
@@ -1833,10 +1832,21 @@
} else {
switch (xop) {
case 0x20: /* taddcc */
+ gen_op_tadd_T1_T0_cc();
+ gen_movl_T0_reg(rd);
+ break;
case 0x21: /* tsubcc */
+ gen_op_tsub_T1_T0_cc();
+ gen_movl_T0_reg(rd);
+ break;
case 0x22: /* taddcctv */
+ gen_op_tadd_T1_T0_ccTV();
+ gen_movl_T0_reg(rd);
+ break;
case 0x23: /* tsubcctv */
- goto illegal_insn;
+ gen_op_tsub_T1_T0_ccTV();
+ gen_movl_T0_reg(rd);
+ break;
case 0x24: /* mulscc */
gen_op_mulscc_T1_T0();
gen_movl_T0_reg(rd);
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
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