[Qemu-devel] [PATCH][SPARC] Doubleword alignment for floating point instructions

[Qemu-devel] [PATCH][SPARC] Doubleword alignment for floating point instructions

[Aurelien Jarno]

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Hi all,

According to the SPARC v8 manual, floating point instructions that
operate on doublewords should be aligned. The processor should
ignore the least significant bit of the register number, and may 
generate a trap.

Very few real CPU are actually generating a trap, so the attached patch
simply make the emulated CPU to ignore the smaller bit.

Note that on SPARC v9, this bit is actually used as the most significant
bit.

Bye,
Aurelien

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

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diff -u -d -p -r1.44 translate.c
--- qemu.orig/target-sparc/translate.c	1 Apr 2007 16:23:36 -0000	1.44
+++ qemu/target-sparc/translate.c	5 Apr 2007 17:41:37 -0000
@@ -90,7 +89,7 @@ enum {
 #ifdef TARGET_SPARC64
 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
 #else
-#define DFPREG(r) (r)
+#define DFPREG(r) (r & 0x1e)
 #endif
 
 #ifdef USE_DIRECT_JUMP