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From: Aurelien Jarno <aurelien@aurel32.net>
To: Blue Swirl <blueswir1@hotmail.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH][SPARC] Full implementation of IEEE exceptions
Date: Fri, 6 Apr 2007 09:06:01 +0200	[thread overview]
Message-ID: <20070406070601.GA6962@farad.aurel32.net> (raw)
In-Reply-To: <BAY143-F23D6BE94DB1EA4D4003526FF640@phx.gbl>

On Fri, Apr 06, 2007 at 08:22:21AM +0200, Blue Swirl wrote:
> >The attached patch fully implements IEEE exceptions on the SPARC target.
> 
> Nice work, thank you. Do you know of any code that uses the exceptions?

I guess no code is using IEEE exceptions to generate a trap, because 
defining a signal handler for SIGFPE is highly non-standard. However a 
few programs are querying FSR to check the AEXC flags after a sequence 
of floating point instructions. This is the case for example of the SUN 
Java J2RE.

> The flags enabling exceptions could be recorded to TB flags so that the 
> check code is generated only when needed, see cpu-exec.c:180.

Well I doubt it is possible, because check_ieee_exceptions() generates a
trap if the TEM flags in the FSR register are set, but also update the 
AEXC flag in FSR. I even doubt lazy FSR is possible here, because it 
accumulates the exceptions of all floating points instructions since 
those flags are cleared.

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

  reply	other threads:[~2007-04-06  7:09 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-04-05 19:16 [Qemu-devel] [PATCH][SPARC] Full implementation of IEEE exceptions Aurelien Jarno
2007-04-06  6:22 ` Blue Swirl
2007-04-06  7:06   ` Aurelien Jarno [this message]
2007-04-06  6:47 ` Blue Swirl
2007-04-06  7:07   ` Aurelien Jarno

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