From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HZia0-0007Jq-6j for qemu-devel@nongnu.org; Fri, 06 Apr 2007 03:09:52 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HZiZy-0007IP-Gd for qemu-devel@nongnu.org; Fri, 06 Apr 2007 03:09:51 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HZiZy-0007I2-8s for qemu-devel@nongnu.org; Fri, 06 Apr 2007 03:09:50 -0400 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HZiWU-00071j-Qf for qemu-devel@nongnu.org; Fri, 06 Apr 2007 03:06:15 -0400 Date: Fri, 6 Apr 2007 09:06:01 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH][SPARC] Full implementation of IEEE exceptions Message-ID: <20070406070601.GA6962@farad.aurel32.net> References: <20070405191644.GA15575@amd64.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org On Fri, Apr 06, 2007 at 08:22:21AM +0200, Blue Swirl wrote: > >The attached patch fully implements IEEE exceptions on the SPARC target. > > Nice work, thank you. Do you know of any code that uses the exceptions? I guess no code is using IEEE exceptions to generate a trap, because defining a signal handler for SIGFPE is highly non-standard. However a few programs are querying FSR to check the AEXC flags after a sequence of floating point instructions. This is the case for example of the SUN Java J2RE. > The flags enabling exceptions could be recorded to TB flags so that the > check code is generated only when needed, see cpu-exec.c:180. Well I doubt it is possible, because check_ieee_exceptions() generates a trap if the TEM flags in the FSR register are set, but also update the AEXC flag in FSR. I even doubt lazy FSR is possible here, because it accumulates the exceptions of all floating points instructions since those flags are cleared. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net