[Qemu-devel] [PATCH][MIPS] Fix 64-bit address computation from base + offset

[Qemu-devel] [PATCH][MIPS] Fix 64-bit address computation from base + offset

[Aurelien Jarno]

Hi all,

While trying to get a 64-bit kernel booting on the emulated Malta board,
I have noticed that load/store addresses are not correctly computed on a
64-bit target. Using gen_op_add() to compute the effective base + offset
address strip it to 32-bit.

The patch below fixes that by defining a new gen_op_addr_add() that
don't cast the result to 32-bit, except in user mode with Status_UX = 0.
In that case the MIPS64 PRA manual explicitely says that it should be
casted to 32-bit and signed extended to 64-bit.

Bye,
Aurelien


Index: target-mips/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/op.c,v
retrieving revision 1.45
diff -u -d -p -r1.45 op.c
--- target-mips/op.c	7 May 2007 13:55:33 -0000	1.45
+++ target-mips/op.c	8 May 2007 21:50:52 -0000
@@ -289,6 +289,22 @@ void op_store_LO (void)
 #undef MEMSUFFIX
 #endif
 
+/* Addresses computation */
+void op_addr_add (void)
+{
+/* For compatibility with 32-bit code, data reference in user mode
+   with Status_UX = 0 should be casted to 32-bit and sign extended. 
+   See the MIPS64 PRA manual, section 4.10. */
+#ifdef TARGET_MIPS64
+    if ((env->CP0_Status & (1 << CP0St_UM)) && 
+        ! (env->CP0_Status & (1 << CP0St_UX)))
+        T0 = (int64_t)(int32_t)(T0 + T1);
+    else
+#endif
+        T0 += T1;
+    RETURN();
+}
+
 /* Arithmetic */
 void op_add (void)
 {
Index: target-mips/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.69
diff -u -d -p -r1.69 translate.c
--- target-mips/translate.c	7 May 2007 13:55:33 -0000	1.69
+++ target-mips/translate.c	8 May 2007 21:50:53 -0000
@@ -719,7 +719,7 @@ static void gen_ldst (DisasContext *ctx,
     } else {
         gen_op_load_gpr_T0(base);
         gen_op_set_T1(offset);
-        gen_op_add();
+        gen_op_addr_add();
     }
     /* Don't do NOP if destination is zero: we must perform the actual
      * memory access
@@ -868,7 +868,7 @@ static void gen_flt_ldst (DisasContext *
     } else {
         gen_op_load_gpr_T0(base);
         gen_op_set_T1(offset);
-        gen_op_add();
+        gen_op_addr_add();
     }
     /* Don't do NOP if destination is zero: we must perform the actual
      * memory access

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net