From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HlXu6-00043C-GS for qemu-devel@nongnu.org; Tue, 08 May 2007 18:11:30 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HlXu5-0003zW-3H for qemu-devel@nongnu.org; Tue, 08 May 2007 18:11:30 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HlXu4-0003zL-Ud for qemu-devel@nongnu.org; Tue, 08 May 2007 18:11:28 -0400 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HlXmw-00064t-EV for qemu-devel@nongnu.org; Tue, 08 May 2007 18:04:06 -0400 Received: from amd64.aurel32.net ([2001:618:400:fc13:216:3eff:fe00:1009]) by mail.aurel32.net with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1HlXmr-0003gh-9g for qemu-devel@nongnu.org; Wed, 09 May 2007 00:04:01 +0200 Received: from aurel32 by amd64.aurel32.net with local (Exim 4.67) (envelope-from ) id 1HlXmr-0007JR-4V for qemu-devel@nongnu.org; Wed, 09 May 2007 00:04:01 +0200 Date: Wed, 9 May 2007 00:04:01 +0200 From: Aurelien Jarno Message-ID: <20070508220400.GA27192@amd64.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Subject: [Qemu-devel] [PATCH][MIPS] Fix 64-bit address computation from base + offset Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi all, While trying to get a 64-bit kernel booting on the emulated Malta board, I have noticed that load/store addresses are not correctly computed on a 64-bit target. Using gen_op_add() to compute the effective base + offset address strip it to 32-bit. The patch below fixes that by defining a new gen_op_addr_add() that don't cast the result to 32-bit, except in user mode with Status_UX = 0. In that case the MIPS64 PRA manual explicitely says that it should be casted to 32-bit and signed extended to 64-bit. Bye, Aurelien Index: target-mips/op.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/op.c,v retrieving revision 1.45 diff -u -d -p -r1.45 op.c --- target-mips/op.c 7 May 2007 13:55:33 -0000 1.45 +++ target-mips/op.c 8 May 2007 21:50:52 -0000 @@ -289,6 +289,22 @@ void op_store_LO (void) #undef MEMSUFFIX #endif +/* Addresses computation */ +void op_addr_add (void) +{ +/* For compatibility with 32-bit code, data reference in user mode + with Status_UX = 0 should be casted to 32-bit and sign extended. + See the MIPS64 PRA manual, section 4.10. */ +#ifdef TARGET_MIPS64 + if ((env->CP0_Status & (1 << CP0St_UM)) && + ! (env->CP0_Status & (1 << CP0St_UX))) + T0 = (int64_t)(int32_t)(T0 + T1); + else +#endif + T0 += T1; + RETURN(); +} + /* Arithmetic */ void op_add (void) { Index: target-mips/translate.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/translate.c,v retrieving revision 1.69 diff -u -d -p -r1.69 translate.c --- target-mips/translate.c 7 May 2007 13:55:33 -0000 1.69 +++ target-mips/translate.c 8 May 2007 21:50:53 -0000 @@ -719,7 +719,7 @@ static void gen_ldst (DisasContext *ctx, } else { gen_op_load_gpr_T0(base); gen_op_set_T1(offset); - gen_op_add(); + gen_op_addr_add(); } /* Don't do NOP if destination is zero: we must perform the actual * memory access @@ -868,7 +868,7 @@ static void gen_flt_ldst (DisasContext * } else { gen_op_load_gpr_T0(base); gen_op_set_T1(offset); - gen_op_add(); + gen_op_addr_add(); } /* Don't do NOP if destination is zero: we must perform the actual * memory access -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net