From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HlsXz-0006F0-6e for qemu-devel@nongnu.org; Wed, 09 May 2007 16:14:03 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HlsXw-0006Eo-Pf for qemu-devel@nongnu.org; Wed, 09 May 2007 16:14:02 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HlsXw-0006El-Jj for qemu-devel@nongnu.org; Wed, 09 May 2007 16:14:00 -0400 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HlsQh-0000FJ-6W for qemu-devel@nongnu.org; Wed, 09 May 2007 16:06:31 -0400 Received: from amd64.aurel32.net ([2001:618:400:fc13:216:3eff:fe00:1009]) by mail.aurel32.net with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1HlsQf-0005Te-B8 for qemu-devel@nongnu.org; Wed, 09 May 2007 22:06:29 +0200 Received: from aurel32 by amd64.aurel32.net with local (Exim 4.67) (envelope-from ) id 1HlsQf-0004zb-16 for qemu-devel@nongnu.org; Wed, 09 May 2007 22:06:29 +0200 Date: Wed, 9 May 2007 22:06:28 +0200 From: Aurelien Jarno Message-ID: <20070509200628.GA18367@amd64.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Subject: [Qemu-devel] [PATCH][MIPS] Fix for the scd instruction Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, The scd instruction is not correctly implemented. In op_mem.c a 1 or a 0 is returned in T0 depending on the success or not of the RMW sequence. However in translate.c, the result is never copied back to the register. The trivial patch below fixes that. Please also find below a boot of a 64-bit kernel on the MIPS target. I guess the next step is to implement 64-bit TLB. Bye, Aurelien (qemu) Linux version 2.6.21.1 (aurel32@i386) (gcc version 4.1.1 ()) #1 Sun May 6 21:43:32 CEST 2007 LINUX started... CPU revision is: 00000400 FPU revision is: 00730400 registering PCI controller with io_map_base unset Determined physical RAM map: memory: 0000000000001000 @ 0000000000000000 (reserved) memory: 00000000000ef000 @ 0000000000001000 (ROM data) memory: 0000000000464000 @ 00000000000f0000 (reserved) memory: 0000000007aab000 @ 0000000000554000 (usable) Wasting 76384 bytes for tracking 1364 unused pages Initrd not found or empty - disabling initrd Built 1 zonelists. Total pages: 32320 Kernel command line: root=/dev/hda1 console=ttyS0 Primary instruction cache 4kB, physically tagged, direct mapped, linesize 16 bytes. Primary data cache 16kB, direct mapped, linesize 16 bytes. Unified secondary cache 128kB direct mapped, linesize 16 bytes. Synthesized TLB refill handler (39 instructions). Synthesized TLB load handler fastpath (51 instructions). Synthesized TLB store handler fastpath (51 instructions). Synthesized TLB modify handler fastpath (50 instructions). PID hash table entries: 512 (order: 9, 4096 bytes) CPU frequency 200.05 MHz Using 100.023 MHz high precision timer. Index: target-mips/translate.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/translate.c,v retrieving revision 1.70 diff -u -d -p -r1.70 translate.c --- target-mips/translate.c 9 May 2007 09:33:33 -0000 1.70 +++ target-mips/translate.c 9 May 2007 20:00:54 -0000 @@ -745,6 +745,7 @@ static void gen_ldst (DisasContext *ctx, save_cpu_state(ctx, 1); GEN_LOAD_REG_TN(T1, rt); op_ldst(scd); + GEN_STORE_TN_REG(rt, T0); opn = "scd"; break; case OPC_LDL: -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net