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From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] Timers
Date: Wed, 23 May 2007 18:58:28 +0100
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To: qemu-devel@nongnu.org
Cc: "George G. Davis" <davis_g@comcast.net>

> > Nice idea! On Sparc the timer can be configured to work in 64-bit
> > mode, so could the ptimer_get/set_count be changed to use 64-bit
> > values?
>
> Perhaps the width could be made runtime configurable, e.g. 16, 24, 32,
> 64-bits as required for a given system, since there are other targets
> which may need differring widths (mind I haven't looked all too closely
> at the code to see if it already handles this : ).  Likewise, perhaps
> up/down count can also be made runtime configurable, since, again, some
> targets implement up counters.  The logic is all the same in that
> case, with just a difference in sign...

I don't think there's any point. A 64-bit countdown timer is sufficient to 
implement everything, and I'd expect the overhead is going to minimal. 
Converting a count-down timer into a count-up timer is trivial. The ARM 
timers are actually count-up timers.

Paul