From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HvKFP-0001cw-HQ for qemu-devel@nongnu.org; Mon, 04 Jun 2007 17:37:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HvKFN-0001bO-Vg for qemu-devel@nongnu.org; Mon, 04 Jun 2007 17:37:55 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HvKFN-0001bI-QT for qemu-devel@nongnu.org; Mon, 04 Jun 2007 17:37:53 -0400 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HvKFN-0008U9-7h for qemu-devel@nongnu.org; Mon, 04 Jun 2007 17:37:53 -0400 Received: from farad.aurel32.net ([2001:618:400:fc13:216:3eff:fe00:100c]) by mail.aurel32.net with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1HvKFH-0007L7-SC for qemu-devel@nongnu.org; Mon, 04 Jun 2007 23:37:47 +0200 Received: from aurel32 by farad.aurel32.net with local (Exim 4.63) (envelope-from ) id 1HvKFH-0002HZ-Hm for qemu-devel@nongnu.org; Mon, 04 Jun 2007 23:37:47 +0200 Date: Mon, 4 Jun 2007 23:37:47 +0200 From: Aurelien Jarno Message-ID: <20070604213747.GA8768@farad.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Subject: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi all, The patch below fixes the Status_rw_bitmask values for 64-bit CPUs: - Reverse endianess is currently not implemented, the RE bit should not be writable. - 64-bit is implemented, the PX bit should be writable. Bye, Aurelien Index: target-mips/translate_init.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v retrieving revision 1.13 diff -u -d -p -r1.13 translate_init.c --- target-mips/translate_init.c 1 Jun 2007 21:57:32 -0000 1.13 +++ target-mips/translate_init.c 4 Jun 2007 13:00:30 -0000 @@ -145,7 +145,7 @@ static mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 16, .CCRes = 2, - .Status_rw_bitmask = 0x3678FFFF, + .Status_rw_bitmask = 0x34F8FFFF, /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), }, @@ -161,7 +161,7 @@ static mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, .CCRes = 2, - .Status_rw_bitmask = 0x3278FFFF, + .Status_rw_bitmask = 0x30F8FFFF, }, { .name = "5Kf", @@ -175,7 +175,7 @@ static mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, .CCRes = 2, - .Status_rw_bitmask = 0x3678FFFF, + .Status_rw_bitmask = 0x34F8FFFF, /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), @@ -192,7 +192,7 @@ static mips_def_t mips_defs[] = .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, .CCRes = 2, - .Status_rw_bitmask = 0x36FBFFFF, + .Status_rw_bitmask = 0x34FBFFFF, /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_D) | (1 << FCR0_S) | -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net