* [Qemu-devel] [PATCH] Add parallel memory mapped interface
@ 2007-06-06 19:26 Hervé Poussineau
2007-06-06 20:14 ` Blue Swirl
0 siblings, 1 reply; 3+ messages in thread
From: Hervé Poussineau @ 2007-06-06 19:26 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 287 bytes --]
Hi,
This patch adds a memory-mapped interface to the parallel port emulation. It
is not as complete as I/O interface (no EPP/ECP), but I didn't want to add
lots of code for very little use.
It also cleans up indentation of the file (replaces tabulations by four
spaces)
Hervé
[-- Attachment #2: parallel_mm.diff --]
[-- Type: application/octet-stream, Size: 20105 bytes --]
Index: vl.h
===================================================================
RCS file: /cvsroot/qemu/qemu/vl.h,v
retrieving revision 1.248
diff -u -r1.248 vl.h
--- vl.h 4 Jun 2007 00:31:00 -0000 1.248
+++ vl.h 6 Jun 2007 19:03:26 -0000
@@ -1085,6 +1085,7 @@
typedef struct ParallelState ParallelState;
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
+ParallelState *parallel_mm_init(target_ulong base, int it_shift, qemu_irq irq, CharDriverState *chr);
/* i8259.c */
Index: hw/mips_pica61.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/mips_pica61.c,v
retrieving revision 1.5
diff -u -r1.5 mips_pica61.c
--- hw/mips_pica61.c 30 May 2007 20:46:01 -0000 1.5
+++ hw/mips_pica61.c 6 Jun 2007 19:03:27 -0000
@@ -153,7 +153,7 @@
}
for (i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
- /* FIXME: memory mapped! parallel_init(0x80008000, i8259[17], parallel_hds[i]); */
+ parallel_mm_init(0x80008000, 0, i8259[1], parallel_hds[i]);
}
}
Index: hw/parallel.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/parallel.c,v
retrieving revision 1.6
diff -u -r1.6 parallel.c
--- hw/parallel.c 7 Apr 2007 18:14:41 -0000 1.6
+++ hw/parallel.c 6 Jun 2007 19:03:27 -0000
@@ -71,6 +71,9 @@
int hw_driver;
int epp_timeout;
uint32_t last_read_offset; /* For debugging */
+ /* Memory-mapped interface */
+ target_ulong base;
+ int it_shift;
};
static void parallel_update_irq(ParallelState *s)
@@ -91,29 +94,29 @@
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
- s->dataw = val;
- parallel_update_irq(s);
+ s->dataw = val;
+ parallel_update_irq(s);
break;
case PARA_REG_CTR:
- if ((val & PARA_CTR_INIT) == 0 ) {
- s->status = PARA_STS_BUSY;
- s->status |= PARA_STS_ACK;
- s->status |= PARA_STS_ONLINE;
- s->status |= PARA_STS_ERROR;
- }
- else if (val & PARA_CTR_SELECT) {
- if (val & PARA_CTR_STROBE) {
- s->status &= ~PARA_STS_BUSY;
- if ((s->control & PARA_CTR_STROBE) == 0)
- qemu_chr_write(s->chr, &s->dataw, 1);
- } else {
- if (s->control & PARA_CTR_INTEN) {
- s->irq_pending = 1;
- }
- }
- }
- parallel_update_irq(s);
- s->control = val;
+ if ((val & PARA_CTR_INIT) == 0 ) {
+ s->status = PARA_STS_BUSY;
+ s->status |= PARA_STS_ACK;
+ s->status |= PARA_STS_ONLINE;
+ s->status |= PARA_STS_ERROR;
+ }
+ else if (val & PARA_CTR_SELECT) {
+ if (val & PARA_CTR_STROBE) {
+ s->status &= ~PARA_STS_BUSY;
+ if ((s->control & PARA_CTR_STROBE) == 0)
+ qemu_chr_write(s->chr, &s->dataw, 1);
+ } else {
+ if (s->control & PARA_CTR_INTEN) {
+ s->irq_pending = 1;
+ }
+ }
+ }
+ parallel_update_irq(s);
+ s->control = val;
break;
}
}
@@ -132,52 +135,52 @@
switch(addr) {
case PARA_REG_DATA:
if (s->dataw == val)
- return;
- pdebug("wd%02x\n", val);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
- s->dataw = val;
+ return;
+ pdebug("wd%02x\n", val);
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
+ s->dataw = val;
break;
case PARA_REG_STS:
- pdebug("ws%02x\n", val);
- if (val & PARA_STS_TMOUT)
- s->epp_timeout = 0;
- break;
+ pdebug("ws%02x\n", val);
+ if (val & PARA_STS_TMOUT)
+ s->epp_timeout = 0;
+ break;
case PARA_REG_CTR:
val |= 0xc0;
if (s->control == val)
- return;
- pdebug("wc%02x\n", val);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
- s->control = val;
+ return;
+ pdebug("wc%02x\n", val);
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
+ s->control = val;
break;
case PARA_REG_EPP_ADDR:
- if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
- /* Controls not correct for EPP address cycle, so do nothing */
- pdebug("wa%02x s\n", val);
- else {
- struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
- s->epp_timeout = 1;
- pdebug("wa%02x t\n", val);
- }
- else
- pdebug("wa%02x\n", val);
- }
- break;
+ if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
+ /* Controls not correct for EPP address cycle, so do nothing */
+ pdebug("wa%02x s\n", val);
+ else {
+ struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
+ if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
+ s->epp_timeout = 1;
+ pdebug("wa%02x t\n", val);
+ }
+ else
+ pdebug("wa%02x\n", val);
+ }
+ break;
case PARA_REG_EPP_DATA:
- if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("we%02x s\n", val);
- else {
- struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
- s->epp_timeout = 1;
- pdebug("we%02x t\n", val);
- }
- else
- pdebug("we%02x\n", val);
- }
- break;
+ if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("we%02x s\n", val);
+ else {
+ struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
+ if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
+ s->epp_timeout = 1;
+ pdebug("we%02x t\n", val);
+ }
+ else
+ pdebug("we%02x\n", val);
+ }
+ break;
}
}
@@ -188,20 +191,20 @@
uint16_t eppdata = cpu_to_le16(val);
int err;
struct ParallelIOArg ioarg = {
- .buffer = &eppdata, .count = sizeof(eppdata)
+ .buffer = &eppdata, .count = sizeof(eppdata)
};
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("we%04x s\n", val);
- return;
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("we%04x s\n", val);
+ return;
}
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
- s->epp_timeout = 1;
- pdebug("we%04x t\n", val);
+ s->epp_timeout = 1;
+ pdebug("we%04x t\n", val);
}
else
- pdebug("we%04x\n", val);
+ pdebug("we%04x\n", val);
}
static void
@@ -211,20 +214,20 @@
uint32_t eppdata = cpu_to_le32(val);
int err;
struct ParallelIOArg ioarg = {
- .buffer = &eppdata, .count = sizeof(eppdata)
+ .buffer = &eppdata, .count = sizeof(eppdata)
};
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("we%08x s\n", val);
- return;
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("we%08x s\n", val);
+ return;
}
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
- s->epp_timeout = 1;
- pdebug("we%08x t\n", val);
+ s->epp_timeout = 1;
+ pdebug("we%08x t\n", val);
}
else
- pdebug("we%08x\n", val);
+ pdebug("we%08x\n", val);
}
static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
@@ -235,25 +238,25 @@
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
- if (s->control & PARA_CTR_DIR)
- ret = s->datar;
- else
- ret = s->dataw;
+ if (s->control & PARA_CTR_DIR)
+ ret = s->datar;
+ else
+ ret = s->dataw;
break;
case PARA_REG_STS:
- ret = s->status;
- s->irq_pending = 0;
- if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
- /* XXX Fixme: wait 5 microseconds */
- if (s->status & PARA_STS_ACK)
- s->status &= ~PARA_STS_ACK;
- else {
- /* XXX Fixme: wait 5 microseconds */
- s->status |= PARA_STS_ACK;
- s->status |= PARA_STS_BUSY;
- }
- }
- parallel_update_irq(s);
+ ret = s->status;
+ s->irq_pending = 0;
+ if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
+ /* XXX Fixme: wait 5 microseconds */
+ if (s->status & PARA_STS_ACK)
+ s->status &= ~PARA_STS_ACK;
+ else {
+ /* XXX Fixme: wait 5 microseconds */
+ s->status |= PARA_STS_ACK;
+ s->status |= PARA_STS_BUSY;
+ }
+ }
+ parallel_update_irq(s);
break;
case PARA_REG_CTR:
ret = s->control;
@@ -270,63 +273,63 @@
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
- if (s->last_read_offset != addr || s->datar != ret)
- pdebug("rd%02x\n", ret);
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
+ if (s->last_read_offset != addr || s->datar != ret)
+ pdebug("rd%02x\n", ret);
s->datar = ret;
break;
case PARA_REG_STS:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
- ret &= ~PARA_STS_TMOUT;
- if (s->epp_timeout)
- ret |= PARA_STS_TMOUT;
- if (s->last_read_offset != addr || s->status != ret)
- pdebug("rs%02x\n", ret);
- s->status = ret;
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
+ ret &= ~PARA_STS_TMOUT;
+ if (s->epp_timeout)
+ ret |= PARA_STS_TMOUT;
+ if (s->last_read_offset != addr || s->status != ret)
+ pdebug("rs%02x\n", ret);
+ s->status = ret;
break;
case PARA_REG_CTR:
/* s->control has some bits fixed to 1. It is zero only when
- it has not been yet written to. */
- if (s->control == 0) {
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
- if (s->last_read_offset != addr)
- pdebug("rc%02x\n", ret);
- s->control = ret;
- }
- else {
- ret = s->control;
- if (s->last_read_offset != addr)
- pdebug("rc%02x\n", ret);
- }
+ it has not been yet written to. */
+ if (s->control == 0) {
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
+ if (s->last_read_offset != addr)
+ pdebug("rc%02x\n", ret);
+ s->control = ret;
+ }
+ else {
+ ret = s->control;
+ if (s->last_read_offset != addr)
+ pdebug("rc%02x\n", ret);
+ }
break;
case PARA_REG_EPP_ADDR:
- if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
- /* Controls not correct for EPP addr cycle, so do nothing */
- pdebug("ra%02x s\n", ret);
- else {
- struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
- s->epp_timeout = 1;
- pdebug("ra%02x t\n", ret);
- }
- else
- pdebug("ra%02x\n", ret);
- }
- break;
+ if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
+ /* Controls not correct for EPP addr cycle, so do nothing */
+ pdebug("ra%02x s\n", ret);
+ else {
+ struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
+ if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
+ s->epp_timeout = 1;
+ pdebug("ra%02x t\n", ret);
+ }
+ else
+ pdebug("ra%02x\n", ret);
+ }
+ break;
case PARA_REG_EPP_DATA:
- if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("re%02x s\n", ret);
- else {
- struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
- s->epp_timeout = 1;
- pdebug("re%02x t\n", ret);
- }
- else
- pdebug("re%02x\n", ret);
- }
- break;
+ if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("re%02x s\n", ret);
+ else {
+ struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
+ if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
+ s->epp_timeout = 1;
+ pdebug("re%02x t\n", ret);
+ }
+ else
+ pdebug("re%02x\n", ret);
+ }
+ break;
}
s->last_read_offset = addr;
return ret;
@@ -340,22 +343,22 @@
uint16_t eppdata = ~0;
int err;
struct ParallelIOArg ioarg = {
- .buffer = &eppdata, .count = sizeof(eppdata)
+ .buffer = &eppdata, .count = sizeof(eppdata)
};
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("re%04x s\n", eppdata);
- return eppdata;
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("re%04x s\n", eppdata);
+ return eppdata;
}
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le16_to_cpu(eppdata);
if (err) {
- s->epp_timeout = 1;
- pdebug("re%04x t\n", ret);
+ s->epp_timeout = 1;
+ pdebug("re%04x t\n", ret);
}
else
- pdebug("re%04x\n", ret);
+ pdebug("re%04x\n", ret);
return ret;
}
@@ -367,22 +370,22 @@
uint32_t eppdata = ~0U;
int err;
struct ParallelIOArg ioarg = {
- .buffer = &eppdata, .count = sizeof(eppdata)
+ .buffer = &eppdata, .count = sizeof(eppdata)
};
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
- /* Controls not correct for EPP data cycle, so do nothing */
- pdebug("re%08x s\n", eppdata);
- return eppdata;
+ /* Controls not correct for EPP data cycle, so do nothing */
+ pdebug("re%08x s\n", eppdata);
+ return eppdata;
}
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le32_to_cpu(eppdata);
if (err) {
- s->epp_timeout = 1;
- pdebug("re%08x t\n", ret);
+ s->epp_timeout = 1;
+ pdebug("re%08x t\n", ret);
}
else
- pdebug("re%08x\n", ret);
+ pdebug("re%08x\n", ret);
return ret;
}
@@ -400,15 +403,8 @@
return ret;
}
-/* If fd is zero, it means that the parallel device uses the console */
-ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
+static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
{
- ParallelState *s;
- uint8_t dummy;
-
- s = qemu_mallocz(sizeof(ParallelState));
- if (!s)
- return NULL;
s->datar = ~0;
s->dataw = ~0;
s->status = PARA_STS_BUSY;
@@ -423,25 +419,113 @@
s->hw_driver = 0;
s->epp_timeout = 0;
s->last_read_offset = ~0U;
+}
+
+/* If fd is zero, it means that the parallel device uses the console */
+ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
+{
+ ParallelState *s;
+ uint8_t dummy;
+
+ s = qemu_mallocz(sizeof(ParallelState));
+ if (!s)
+ return NULL;
+ parallel_reset(s, irq, chr);
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
- s->status = dummy;
+ s->status = dummy;
}
if (s->hw_driver) {
- register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
- register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
- register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
- register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
- register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
- register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
- register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
- register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
+ register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
+ register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
+ register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
+ register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
+ register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
+ register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
+ register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
+ register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
}
else {
- register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
- register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
+ register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
+ register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
}
return s;
}
+
+/* Memory mapped interface */
+uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+{
+ ParallelState *s = opaque;
+
+ return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
+}
+
+void parallel_mm_writeb (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ ParallelState *s = opaque;
+
+ parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+}
+
+uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+{
+ ParallelState *s = opaque;
+
+ return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+}
+
+void parallel_mm_writew (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ ParallelState *s = opaque;
+
+ parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+}
+
+uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+{
+ ParallelState *s = opaque;
+
+ return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
+}
+
+void parallel_mm_writel (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ ParallelState *s = opaque;
+
+ parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
+}
+
+static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
+ ¶llel_mm_readb,
+ ¶llel_mm_readw,
+ ¶llel_mm_readl,
+};
+
+static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
+ ¶llel_mm_writeb,
+ ¶llel_mm_writew,
+ ¶llel_mm_writel,
+};
+
+/* If fd is zero, it means that the parallel device uses the console */
+ParallelState *parallel_mm_init(target_ulong base, int it_shift, qemu_irq irq, CharDriverState *chr)
+{
+ ParallelState *s;
+ int io_sw;
+
+ s = qemu_mallocz(sizeof(ParallelState));
+ if (!s)
+ return NULL;
+ parallel_reset(s, irq, chr);
+ s->base = base;
+ s->it_shift = it_shift;
+
+ io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
+ cpu_register_physical_memory(base, 8 << it_shift, io_sw);
+ return s;
+}
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] Add parallel memory mapped interface
2007-06-06 19:26 [Qemu-devel] [PATCH] Add parallel memory mapped interface Hervé Poussineau
@ 2007-06-06 20:14 ` Blue Swirl
2007-06-06 22:36 ` Paul Brook
0 siblings, 1 reply; 3+ messages in thread
From: Blue Swirl @ 2007-06-06 20:14 UTC (permalink / raw)
To: qemu-devel, hpoussin
On 6/6/07, Hervé Poussineau <hpoussin@reactos.org> wrote:
> Hi,
>
> This patch adds a memory-mapped interface to the parallel port emulation. It
> is not as complete as I/O interface (no EPP/ECP), but I didn't want to add
> lots of code for very little use.
> It also cleans up indentation of the file (replaces tabulations by four
> spaces)
Please don't use target_ulong in device drivers, but
target_phys_addr_t for physical addresses. I don't know about IO
addresses, uint32_t?
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] Add parallel memory mapped interface
2007-06-06 20:14 ` Blue Swirl
@ 2007-06-06 22:36 ` Paul Brook
0 siblings, 0 replies; 3+ messages in thread
From: Paul Brook @ 2007-06-06 22:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, hpoussin
On Wednesday 06 June 2007, Blue Swirl wrote:
> On 6/6/07, Hervé Poussineau <hpoussin@reactos.org> wrote:
> > Hi,
> >
> > This patch adds a memory-mapped interface to the parallel port emulation.
> > It is not as complete as I/O interface (no EPP/ECP), but I didn't want to
> > add lots of code for very little use.
> > It also cleans up indentation of the file (replaces tabulations by four
> > spaces)
IMHO it's a bad idea to combine writespace cleanups with actual changes.
It makes the patch much larger and more confusing than it needs to be.
> Please don't use target_ulong in device drivers, but
> target_phys_addr_t for physical addresses. I don't know about IO
> addresses, uint32_t?
"int" is appropriate for IO port addresses.
This is what the register_ioport_{read,write} routines use.
Paul
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2007-06-06 22:36 UTC | newest]
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2007-06-06 19:26 [Qemu-devel] [PATCH] Add parallel memory mapped interface Hervé Poussineau
2007-06-06 20:14 ` Blue Swirl
2007-06-06 22:36 ` Paul Brook
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