From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HypYa-0004pZ-SX for qemu-devel@nongnu.org; Thu, 14 Jun 2007 09:40:12 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HypYZ-0004pN-IC for qemu-devel@nongnu.org; Thu, 14 Jun 2007 09:40:12 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HypYZ-0004pK-BL for qemu-devel@nongnu.org; Thu, 14 Jun 2007 09:40:11 -0400 Received: from wx-out-0506.google.com ([66.249.82.239]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1HypYY-00014z-Nu for qemu-devel@nongnu.org; Thu, 14 Jun 2007 09:40:11 -0400 Received: by wx-out-0506.google.com with SMTP id t15so536334wxc for ; Thu, 14 Jun 2007 06:40:09 -0700 (PDT) Date: Thu, 14 Jun 2007 21:41:36 +0800 From: amateur Subject: Re: [Qemu-devel] CPUTLBEntry Question Message-ID: <20070614134136.GA6825@163.com> References: <812074ac0706131325t578dfd5eiaa5836b160a24679@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <812074ac0706131325t578dfd5eiaa5836b160a24679@mail.gmail.com> Reply-To: amateur , qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Wed, Jun 13, 2007 at 04:25:07PM -0400, Ryan Riley wrote: > typedef struct CPUTLBEntry { > /* bit 31 to TARGET_PAGE_BITS : virtual address > bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io > zone number > bit 3 : indicates that the entry is invalid > bit 2..0 : zero > */ > target_ulong addr_read; > target_ulong addr_write; > target_ulong addr_code; > /* addend to virtual address to get physical address */ > target_phys_addr_t addend; > } CPUTLBEntry; > > If I change it to add another member, like so.. > > typedef struct CPUTLBEntry { > /* New member */ > target_phys_addr_t blah; > } CPUTLBEntry; > > then QEMU crashes on startup. (It also crashes if I put that blah > entry on the beginning instead of the end.) I'm sure there's code > somewhere that must be making assumptions about the size of TLB entry, > but I'm at a loss for finding it. (I have noticed that the assembly > code in softmmu_header.h indexes to the addend based on addr_read or > addr_write, but adding a new member to the end of the structure > shouldn't impact that, right?) ------------------------- The softmmu_header.h code does assume each TLB entry has a fixed size of (2^CPU_TLB_ENTRY_BITS) bytes. Not only the assembly code, but also the C code assume this. So if you want to add new members into CPUTLBEntry, add the new member at the end of the data structure, and adjust CPU_TLB_ENTRY_BITS accordingly. Best Regards Tianlei Zhao -- Don't look back, the lemmings are gaining on you.