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From: amateur <tianlei.zhao@gmail.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] CPUTLBEntry Question
Date: Fri, 15 Jun 2007 09:47:53 +0800	[thread overview]
Message-ID: <20070615014753.GA3328@163.com> (raw)
In-Reply-To: <f43fc5580706140700p43bc3e30i81e8e2f529b90b32@mail.gmail.com>

On Thu, Jun 14, 2007 at 05:00:32PM +0300, Blue Swirl wrote:
> On 6/14/07, amateur <tianlei.zhao@gmail.com> wrote:
> >The softmmu_header.h code does assume each TLB entry has a fixed size
> >of (2^CPU_TLB_ENTRY_BITS) bytes. Not only the assembly code, but also
> >the C code assume this. So if you want to add new members into
> >CPUTLBEntry, add the new member at the end of the data structure, and
> >adjust CPU_TLB_ENTRY_BITS accordingly.
> 
> No, on Sparc32 target_ulong is 32 bits (on 32-bit host) but
> target_phys_addr_t is 64 bits. That makes the structure size 20 bytes.
> Everything still works.
-------------------------
Oh, yes. It's my fault. I confused CPU_TLB_SIZE and
CPU_TLB_ENTRY_BITS. Paul Brook is right. The C code works with any
CPUTLBEntry layout.

-- 
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      reply	other threads:[~2007-06-15  1:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-06-13 20:25 [Qemu-devel] CPUTLBEntry Question Ryan Riley
2007-06-14 13:22 ` Paul Brook
2007-06-14 19:31   ` Ryan Riley
2007-06-14 13:41 ` amateur
2007-06-14 14:00   ` Blue Swirl
2007-06-15  1:47     ` amateur [this message]

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