From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Hz0tT-00017U-8I for qemu-devel@nongnu.org; Thu, 14 Jun 2007 21:46:31 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Hz0tQ-00017H-JC for qemu-devel@nongnu.org; Thu, 14 Jun 2007 21:46:29 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Hz0tQ-00017E-DK for qemu-devel@nongnu.org; Thu, 14 Jun 2007 21:46:28 -0400 Received: from wa-out-1112.google.com ([209.85.146.179]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Hz0tP-0000Kw-QR for qemu-devel@nongnu.org; Thu, 14 Jun 2007 21:46:28 -0400 Received: by wa-out-1112.google.com with SMTP id k22so925875waf for ; Thu, 14 Jun 2007 18:46:26 -0700 (PDT) Date: Fri, 15 Jun 2007 09:47:53 +0800 From: amateur Subject: Re: [Qemu-devel] CPUTLBEntry Question Message-ID: <20070615014753.GA3328@163.com> References: <812074ac0706131325t578dfd5eiaa5836b160a24679@mail.gmail.com> <20070614134136.GA6825@163.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: Reply-To: amateur , qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Jun 14, 2007 at 05:00:32PM +0300, Blue Swirl wrote: > On 6/14/07, amateur wrote: > >The softmmu_header.h code does assume each TLB entry has a fixed size > >of (2^CPU_TLB_ENTRY_BITS) bytes. Not only the assembly code, but also > >the C code assume this. So if you want to add new members into > >CPUTLBEntry, add the new member at the end of the data structure, and > >adjust CPU_TLB_ENTRY_BITS accordingly. >=20 > No, on Sparc32 target_ulong is 32 bits (on 32-bit host) but > target_phys_addr_t is 64 bits. That makes the structure size 20 bytes. > Everything still works. ------------------------- Oh, yes. It's my fault. I confused CPU_TLB_SIZE and CPU_TLB_ENTRY_BITS. Paul Brook is right. The C code works with any CPUTLBEntry layout. --=20 =1B[32m=E9=A2=98=E7=9B=AE:=E3=80=8A=E6=9D=91=E8=A1=8C=E3=80=8B=1B[m =1B[33m=E4=BD=9C=E8=80=85:=E7=8E=8B=E7=A6=B9=E7=A7=B0=EF=BC=88=E7=B9=81=E4= =BD=93=E2=80=9C=E7=A7=B0=E2=80=9D=EF=BC=8C=E6=8D=A2=E2=80=9C=E4=BA=BB=E2=80= =9D=E6=97=81=EF=BC=89=EF=BC=88=EF=BC=99=EF=BC=95=EF=BC=94=EF=BC=8D=EF=BC=91= =EF=BC=90=EF=BC=90=EF=BC=91=EF=BC=89=1B[m =E9=A9=AC=E7=A9=BF=E5=B1=B1=E5=BE=84=E8=8F=8A=E5=88=9D=E9=BB=84=EF=BC=8C=E4= =BF=A1=E9=A9=AC=E6=82=A0=E6=82=A0=E9=87=8E=E5=85=B4=E9=95=BF=E3=80=82 =E4=B8=87=E5=A3=91=E6=9C=89=E5=A3=B0=E5=90=AB=E6=99=9A=E7=B1=81=EF=BC=8C=E6= =95=B0=E5=B3=B0=E6=97=A0=E8=AF=AD=E7=AB=8B=E6=96=9C=E9=98=B3=E3=80=82 =E6=A3=A0=E6=A2=A8=E5=8F=B6=E8=90=BD=E8=83=AD=E8=84=82=E8=89=B2=EF=BC=8C=E8= =8D=9E=E9=BA=A6=E8=8A=B1=E5=BC=80=E7=99=BD=E9=9B=AA=E9=A6=99=E3=80=82 =E4=BD=95=E4=BA=8B=E5=90=9F=E4=BD=99=E5=BF=BD=E6=83=86=E6=80=85=EF=BC=8C=E6= =9D=91=E6=A1=A5=E5=8E=9F=E6=A0=91=E4=BC=BC=E5=90=BE=E4=B9=A1=E3=80=82