From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Hzl9V-0004xo-8Z for qemu-devel@nongnu.org; Sat, 16 Jun 2007 23:10:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Hzl9Q-0004ww-Bq for qemu-devel@nongnu.org; Sat, 16 Jun 2007 23:10:07 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Hzl9Q-0004wm-1S for qemu-devel@nongnu.org; Sat, 16 Jun 2007 23:10:04 -0400 Received: from wx-out-0506.google.com ([66.249.82.227]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Hzl9P-00067o-M2 for qemu-devel@nongnu.org; Sat, 16 Jun 2007 23:10:03 -0400 Received: by wx-out-0506.google.com with SMTP id t15so1210751wxc for ; Sat, 16 Jun 2007 20:10:03 -0700 (PDT) Date: Sun, 17 Jun 2007 11:11:36 +0800 From: amateur Subject: Re: [Qemu-devel] TB Chaining NOT Reset on TLB Flush?? Message-ID: <20070617031136.GA3425@163.com> References: <20070616132206.GA7968@163.com> <200706161427.06630.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200706161427.06630.paul@codesourcery.com> Reply-To: amateur , qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, Jun 16, 2007 at 02:27:05PM +0100, Paul Brook wrote: > > I read from the Qemu internal documentation this: > > ``When MMU mappings change, only the chaining of the basic > > blocks is reset (i.e. a basic block can no longer jump directly > > to another one).'' > > > > But when I read the code, I find that tlb_flush() doesn't reset the > > chaining between TBs. Is that the intended behaviour?? Won't that > > cause problems on guest context switch?? > > The internals documentation is out of date. TBs are only chained directly when > both source and destination are on the same page. ------------------------- Thank you, Paul. I got it. I can imagine that this decision is based on a performance evaluation, right? But given that TLB flush(mov %cr3, %reg | invlpg) be a relative rare case, it's hard to believe that reset the chaining on each TLB flush would hurt the performance a lot. Can you shed some light on where can I find some profiling data or performance statistics, or links to some discussions on this? -- You will not be elected to public office this year.