From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1I3HiE-0003RK-8k for qemu-devel@nongnu.org; Tue, 26 Jun 2007 16:32:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1I3HiC-0003Qp-DL for qemu-devel@nongnu.org; Tue, 26 Jun 2007 16:32:33 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1I3HiC-0003Qi-6A for qemu-devel@nongnu.org; Tue, 26 Jun 2007 16:32:32 -0400 Received: from hansmi.home.forkbomb.ch ([213.144.146.165]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1I3HiB-0001vC-5t for qemu-devel@nongnu.org; Tue, 26 Jun 2007 16:32:32 -0400 Date: Tue, 26 Jun 2007 22:32:23 +0200 From: Michael Hanselmann Message-ID: <20070626203223.GA10008@hansmi.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] Implement ACPI specs 3.0, 4.7.2.5 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The patch below implements ACPI_ENABLE and ACPI_DISABLE as described in section 4.7.2.5 of the ACPI 3.0 specs. Signed-off-by: Michael Hanselmann Greets, Michael --- Index: hw/acpi.c =================================================================== RCS file: /sources/qemu/qemu/hw/acpi.c,v retrieving revision 1.12 diff -u -b -B -r1.12 acpi.c --- hw/acpi.c 28 May 2007 21:01:02 -0000 1.12 +++ hw/acpi.c 26 Jun 2007 20:29:19 -0000 @@ -54,6 +54,9 @@ #define SUS_EN (1 << 13) +#define ACPI_ENABLE 0xf1 +#define ACPI_DISABLE 0xf0 + #define SMBHSTSTS 0x00 #define SMBHSTCNT 0x02 #define SMBHSTCMD 0x03 @@ -216,6 +219,14 @@ #endif if (addr == 0) { s->apmc = val; + + /* ACPI specs 3.0, 4.7.2.5 */ + if (val == ACPI_ENABLE) { + s->pmcntrl |= SCI_EN; + } else if (val == ACPI_DISABLE) { + s->pmcntrl &= ~SCI_EN; + } + if (s->dev.config[0x5b] & (1 << 1)) { cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); }