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From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework
Date: Tue, 28 Aug 2007 20:43:14 +0100
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To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>

> On second thought, there is a huge difference between a write access
> originating from CPU destined for the device and the device writing to
> main memory. The CPU address could be 0xf000 1000, which may translate
> to a bus address of 0x1000, as an example. The device could write to
> main memory using the same bus address 0x1000, but this time the IOMMU
> would map this to for example 0x1234 5000, or without an IOMMU it
> would be just 0x1000.

While your concern is valid, your example is not.

You can't have the same bus address mapping onto both a device and main 
memory. Your example works if e.g. IO bus address 0x2000 1000 (or worse still 
0xf000 1000) maps onto system memory 0x1234 5000.

Conceptually you can have a separate IOMMU on every bus-bus or bus/host 
bridge, with asymmetric mappings depending where the transaction originates.

I believe some of the newer POWER machines can do this (x86 hardware with this 
capability is not generally available). The ARM PCI host bridge allows 
asymmetric mappings, thought this is simple regions rather than a full IOMMU, 
and is currently not implemented.

Paul