From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IQP7e-0005Of-ML for qemu-devel@nongnu.org; Wed, 29 Aug 2007 11:06:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IQP7d-0005Nl-2G for qemu-devel@nongnu.org; Wed, 29 Aug 2007 11:06:22 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IQP7c-0005Na-S8 for qemu-devel@nongnu.org; Wed, 29 Aug 2007 11:06:20 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IQP7c-0005dy-2O for qemu-devel@nongnu.org; Wed, 29 Aug 2007 11:06:20 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [patch] make qemu work with GCC 4 Date: Wed, 29 Aug 2007 16:06:10 +0100 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200708291606.14173.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Matz , Alexander Graf > I solved that by placing one of the T[012] operands into memory > for HOST_I386, thereby freeing one reg. Here's some justification > of why that doesn't really cost performance: with three free regs > GCC is already spilling like mad in the snippets, we just trade one > of those memory accesses (to stack) with one other mem access to > the cpu_state structure, which will be in cache. Do you have any evidence to support this claim? Last time I did this it cau= sed=20 a significant performance hit. I'd guess that most common ops are simple=20 enough that we don't need more than 3 registers. > --- qemu-0.9.0.cvs.orig/softmmu_header.h > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: "%eax", "%ecx", "%edx", "memory", = "cc"); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: "%eax", "%edx", "memory", "cc"); This change is wrong. The inline asm calls C code which clobbers %ecx. Paul