From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IQUwC-0004se-J2 for qemu-devel@nongnu.org; Wed, 29 Aug 2007 17:18:56 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IQUwA-0004rv-Ln for qemu-devel@nongnu.org; Wed, 29 Aug 2007 17:18:55 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IQUwA-0004ro-Hp for qemu-devel@nongnu.org; Wed, 29 Aug 2007 17:18:54 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IQUwA-0001Bm-0e for qemu-devel@nongnu.org; Wed, 29 Aug 2007 17:18:54 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework Date: Wed, 29 Aug 2007 22:18:46 +0100 References: <200708292139.31760.paul@codesourcery.com> In-Reply-To: <200708292139.31760.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200708292218.49078.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl > If this is the case, it means we don't need anything complicated. Devices > map themselves straight into the system address space at the appropriate > slot address (no plug-n-play to worry about), and device "DMA" goes via the > IOMMU. Further searching by google suggests I may be wrong. The alternative is that the controller maps the 32-bit VA onto a device select+28-bit address, using some as-yet undiscovered mechanism. There are then a couple of different options for how the CPU/memory bus is accessed: a) The IOMMU is one or more slave devices, than feed the 28-bit address possibly plus a few other bits from the device ID into the translation table. This effectively allows you to map a proportion of the SBus 32-bit master VA space onto CPU address space via the IOMMU, and map the remainder onto devices on the same bus. For a system with <=8 slots per bus a fixed mapping using the first 2G as 256Mb for each slot and the top 2G for IOMMU is entirely feasible. b) The 32-bit SBus VA is looked up directly into the IOMMU. Each IOMMU entry can refer to either a CPU address, or a device+28-bit address on the local SBUS. Paul