From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IU1LS-0003RN-H6 for qemu-devel@nongnu.org; Sat, 08 Sep 2007 10:31:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IU1LR-0003Pb-AS for qemu-devel@nongnu.org; Sat, 08 Sep 2007 10:31:33 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IU1LR-0003PB-0W for qemu-devel@nongnu.org; Sat, 08 Sep 2007 10:31:33 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IU1LQ-0000HS-Hs for qemu-devel@nongnu.org; Sat, 08 Sep 2007 10:31:32 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework Date: Sat, 8 Sep 2007 15:31:24 +0100 References: <200708292218.49078.paul@codesourcery.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200709081531.25197.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org > From DMA2.txt, NCR89C100.txt, NCR89C105.txt and turbosparc.pdf I > gather the following: > - CPU and IOMMU always perform slave accesses > - Slave accesses use the 28-bit address bus to select the device I thought device selection was separate from the 28-bit SBus slave address space. ie. each device has exclusive ownership of the whole 28-bit address space, and it's effectively just multiplexing per-slave busses over a single electrical connection. > - Slave accesses are not translated by IOMMU > - NCR master devices (Lance, ESP) use an internal DREQ-style signal to > indicate their need for DMA to their DMA controller > - Master accesses use the 32-bit SBus data signals for both address and > data - DMA controller is the master for NCR89C100+NCR89C105 combination - > Master accesses are translated and controlled by IOMMU > - Slave devices may or may not support master access cycles (not > supported in the NCR case) > - IOMMU can give direct bus access for "intelligent masters" (no devices > known) > > We could model this using two buses: A slave bus between the CPU and > the devices, and a master bus between devices and IOMMU. The slave bus > translates the 36-bit CPU/memory bus addresses to 28-bit SBus bus > addresses. The master bus uses IOMMU to translate 32-bit DVMA > addresses to 36-bit CPU/memory bus addresses. Slave devices are > connected to the slave bus and DREQs. Master devices and DMA > controllers take the DREQs and both buses. Devices register the > address ranges they serve on each bus. IIUC devices never register addresses on the master bus. The only thing that responds on that bus is the IOMMU. > On Sun4c (without IOMMU) there would be just one bus for both purposes > (with the MMU quirk). > > For the Sparc64 PCI bus which has an IOMMU, a similar dual bus > arrangement would be needed. On PC/PPC systems the two buses would be > again one. PCI shouldn't need a dual bus setup. You just have one bus for PCI and one bus for CPU/memory. IMHO the whole point of having a generic bus infrastructure is that we can define address mapping in terms of [asymmetric] translations from one bus address space to another. This isolates teh device from needing to care about bridges and IOMMu. If we're assuming 1:1 or symmetric address space mapping there doesn't seem much point modelling separate busses. Instead push everything into the device registration and DMA routines. Paul